Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 275 / 1898

Volume 2, Part 1: System State and Programming Model 2:27
tb 26 Taken Branch trap – When 1, the successful completion
of a taken branch results in a Taken Branch trap.
rfi
and interruptions can not raise a Taken Branch trap.
When 1, successful completion of a taken IA-32 branch
results in an IA_32_Exception(Debug) trap.
0 data
rt 27 Register stack Translation – When 1, register stack
accesses are translated and access rights are checked.
When 0, register stack accesses use physical
addressing. PSR.dt is ignored for register stack
accesses. The register stack engine must be in
enforced lazy mode (RSC.mode = 00) when modifying
this bit; otherwise, processor behavior is undefined.
During IA-32 instruction execution this bit is ignored and
the register stack is disabled. unchanged data
rv 31:28 reserved
PSR{63:0}
cpl
f
33:32 Current Privilege Level –The current privilege level of
the processor (including IA-32). Controls accessibility to
system registers, instructions and virtual memory
pages. A value of 0 is most privileged, a value of 3 is
least privileged. Written by the
rfi
,
epc
, and
br.ret
instructions. PSR.cpl is unchanged by the
jmpe
and
br.ia
instructions. PSR.cpl cannot be updated by any
IA-32 instructions.
0 rfi
g
is 34 Instruction Set – When 0, Intel Itanium instructions are
executing. When 1, IA-32 instructions are executing.
Written by the
rfi
and
br.ia
instructions and the
IA-32
jmpe
instruction.
0 rfi
g
, br.ia
h
mc 35 Machine Check abort mask – When 1, machine check
aborts are masked. When 0, machine check aborts can
be delivered (including IA-32 instruction set execution).
Processor operation is undefined if PSR.mc is 1 and a
transition is made to execute IA-32 code. unchanged/1
i
rfi
g
it 36 Instruction address Translation – When 1, virtual
instruction addresses are translated and access rights
checked. When 0, instruction accesses use physical
addressing. PSR.it must be 1 when entering IA-32
code, otherwise processor operation is undefined. unchanged/0
j
rfi
g
id 37 Instruction Debug fault disable – When 1, Instruction
Debug faults are disabled on the first restart instruction
in the current bundle.
k
When PSR.id is 1 or EFLAG.rf is
1, IA-32 instruction debug faults are disabled for one
IA-32 instruction. PSR.id and EFLAG.rf are set to 0 after
the successful execution of each IA-32 instruction.
0 rfi
g
da 38 Disable Data Access and Dirty-bit faults – When 1, Data
Access and Dirty-Bit faults are disabled on the first
restart instruction in the current bundle or for the first
mandatory RSE reference following the
rfi
.
k
IA-32
Access/Dirty-bit faults are not affected by PSR.da.
l
0 rfi
g
dd 39 Data Debug fault disable – When 1, Data Debug faults
are disabled on the first restart instruction in the current
bundle or for the first mandatory RSE reference.
k
IA-32
Data Debug traps are not affected by PSR.dd.
l
0 rfi
g
Table 3-2. Processor Status Register Fields (Continued)
Field Bits Description
Interruption
State
Serialization
Required