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Volume 2, Part 2: Context Management
the
epc
until the switch to the kernel backing store has been completed. Additionally,
low-level operating system handlers should not only use IPSR.cpl, but should also
check BSPSTORE, to determine whether they are running on the kernel backing store
(imagine an external interrupt being delivered on the first instruction after the
epc
).
4.4.2
break/rfi
The
break
instruction, when issued in the
i
,
f
, and
m
syllables, specifies an arbitrary
21-bit immediate value. The kernel can choose a specific
break
immediate value to
differentiate system calls from other usage of the
break
instruction (such as debug).
The
break
instruction jumps to the
break
fault handler, which should be a valid address
mapping for each user application, and raises the privilege mode to the most privileged
level.
The system call number is an additional parameter passed to the kernel when invoking
a system call via the
break
instruction. The system call number must reside in a fixed
location. If stored within GR32, then the system call stub must rearrange its input
parameters to map to the register stack starting at GR33. This register jostling can be
avoided by passing the system call number through a scratch static general register or
by using the
break
immediate itself. Additionally, the system call can utilize all eight
input registers of the register stack for system call parameters.
4.4.3
NaT Checking for NaTs in System Calls
In addition to regular range/value checking on system call arguments, Itanium
architecture-based operating systems need to additionally ensure that system call
arguments passed in by a user application do not have any NaT bits set. The following
code fragment can be used:
mov mask = 0xff
clrrrb
;;
// create register stack frame with only output registers for system call args
alloc tmp = ar.pfs, 0, 0, 8, 0
shl mask = mask, syscall_arg_count
;;
mov pr = mask, 0xff00
// define p8 .. p15
;;
cmp.eq p7 = r0, r0
// set p7 to true
;;
// test for NaT bits in the input arguments
(p8)
cmp.eq.and p7 = r32, r32
// and type compare clears p7 if r32 is NaT
(p9)
cmp.eq.and p7 = r33, r33
(p10) cmp.eq.and p7 = r34, r34
(p11) cmp.eq.and p7 = r35, r35
(p12) cmp.eq.and p7 = r36, r36
(p13) cmp.eq.and p7 = r37, r37
(p14) cmp.eq.and p7 = r38, r38
(p15) cmp.eq.and p7 = r39, r39
(p7) br.cond.sptk ok_arguments
// No NaTs found
;;
// p7 was cleared by at least one NaT argument
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...