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Volume 2, Part 2: IA-32 Application Support
9.3
Debugging IA-32 and
Itanium
®
Architecture-based Code
Itanium architecture-based operating systems that want to provide debug support for
both IA-32 and Itanium architecture-based applications, need to be aware of the
differences between taking instruction and data breakpoint exceptions as well as single
step or taken branch traps on Itanium and IA-32 instructions.
9.3.1
Instruction Breakpoints
If an Itanium instruction matches an instruction breakpoint register (IBR) then an
Instruction Debug Fault is delivered on the Itanium Debug vector. To step across a
single Itanium instruction, IPSR.id must be set to one. An IA-32 instruction, however,
that matches an IBR causes an IA-32 Instruction Breakpoint fault which is delivered to
the IA-32 Exception vector (Debug). To step across a single IA-32 instruction, either
IPSR.id or EFLAGS.rf must be set to one.
9.3.2
Data Breakpoints
If an Itanium memory reference matches a data breakpoint register (DBR) then a Data
Debug Fault is delivered on the Itanium Debug vector. To step across a single data
breakpoint, IPSR.dd must be set to one. An IA-32 instruction, however, that matches a
DBR causes an IA-32 Data Breakpoint
trap
which is delivered to the IA-32 Exception
vector (Debug). In other words, the debugger only gets control after the instruction
IA-32 Taken Branch trap
Debug
Relay to debugger.
IA-32 Single Step trap
Debug
Relay to debugger.
IA-32 Invalid Opcode fault
Bad Opcode
Signal application.
IA-32 Intercept
vector (0x6a00)
IA-32 Instruction Intercept fault
Attempted to access
IA-32 paging, MTRRs,
IDT, IA-32 control
registers, IA-32 debug
registers or attempted
to execute IA-32
privileged instructions.
This is not supported on
an Itanium
architecture-based OS.
Signal application.
IA-32 Locked Data Reference
fault
Attempt to reference
misaligned or
uncacheable
semaphore.
Emulation handler if
needed. Refer to
IA-32 System Flag Intercept trap
System Flag intercept
Depends on convention.
IA-32 Gate Intercept trap
Gate/Task transfer
intercept
Depends on convention.
IA-32 Interrupt
vector (0x6b00)
IA-32 Software Interrupt (INT)
trap
Software Interrupt
Depends on convention.
Cannot happen in
Itanium
architecture-based
operating system
IA-32 Double Fault
IA-32 Invalid TSS Fault,
IA-32 Page Fault,
IA-32 Machine Check
N/A
Don’t worry,
Table 9-1.
IA-32 Vectors that need Itanium
®
Architecture-based OS
Support (Continued)
Vector (IVA offset)
Exception Name
Exception Related To
Expected OS Behavior
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...