Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 665 / 1898

Volume 2, Part 1: Processor Abstraction Layer 2:417
PAL_MC_ERROR_INFO
Bus_Check Return Format: The bus_check return format is returned in error_info
when the user requests information on any level of hierarchy of the processor bus
structures as specified in the
level_index input argument. The bus_check return format
must be used to report errors in uncacheable transactions. These errors must not be
reported using the cache_check return format. The bus_check return format is a
bit-field that is described in
Figure 11-22 and Table 11-92 .
Figure 11-22. bus_check Layout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bsi dp hier sev type cc eb ib size
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
pi rp rq tv mcc pv pl iv is reserved
Table 11-92. bus_check Fields
Field Bits Description
size 4:0 Size in bytes of the transaction that caused the machine check abort.
ib 5 Internal bus error
eb 6 External bus error
cc 7 Error occurred during a cache to cache transfer.
type 15:8 Type of transaction that caused the machine check abort.
0 – unknown
1 – partial read
2 – partial write
3 – full line read
4 – full line write
5 – implicit or explicit write-back operation
6 – snoop probe
7 – incoming or outgoing ptc.g
8 – write coalescing transactions
9 – I/O space read
10 – I/O space write
11 – inter-processor interrupt message (IPI)
12 – interrupt acknowledge or external task priority cycle
All other values are reserved
sev 20:16 Bus error severity. The encodings of error severity are platform specific.
hier 22:21 This value indicates which level or bus hierarchy the error occurred in. A value of 0
indicates the first level of hierarchy.
dp 23 A multiple-bit error was detected, and data was poisoned for the incoming cache line.
bsi 31:24 Bus error status information. It describes the type of bus error. This field is processor bus
specific.
reserved 53:32 Reserved
is 54 Instruction set. If this value is set to zero, the instruction that generated the machine
check was an Intel Itanium instruction. If this bit is set to one, the instruction that
generated the machine check was IA-32 instruction.
iv 55 The is field in the bus_check parameter is valid.
pl 57:56 Privilege level. The privilege level of the instruction bundle responsible for generating the
machine check.
pv 58 The pl field of the bus_check parameter is valid.
mcc 59 Machine check corrected: This bit is set to one to indicate that the machine check has
been corrected.
tv 60 Target address is valid: This bit is set to one to indicate that a valid target address has
been logged.