Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 52 / 1898

Volume 1, Part 1: Execution Environment 1:41
The ordering rules above form the context for register dependency restrictions,
memory dependency restrictions and the order of exception reporting. These
dependency restrictions apply only between instructions whose resource reads and
writes are not dynamically disabled by predication.
• Register dependencies: Within an instruction group, read-after-write (RAW) and
write-after-write (WAW) register dependencies are not allowed (except as noted in
“RAW Dependency Special Cases” on page 1:42 and “WAW Dependency Special
Cases” on page 1:43 ). Write-after-read (WAR) register dependencies are allowed
(except as noted in “WAR Dependency Special Cases” on page 1:44 ).
These dependency restrictions apply to both explicit register accesses (from the
instruction’s operands) and implicit register accesses (such as application and
control registers implicitly accessed by certain instructions). Predicate register PR0
is excluded from these register dependency restrictions, since writes to PR0 are
ignored and reads always return 1 (one).
Some system state updates require more stringent requirements than those
described here. See
Section 3.2, “Serialization” on page 2:17 for details.
• Memory dependencies: Within an instruction group, RAW, WAW, and WAR memory
dependencies and ALAT dependencies are allowed. A load will observe the results of
the most recent store to the same memory address. In the event that multiple
stores to the same address are present in the same instruction group, memory will
contain the result of the latest store after execution of the instruction group. A
store following a load to the same address will not affect the data loaded by the
load. Advanced loads, check loads, advanced load checks, stores, and memory
semaphore instructions implicitly access the ALAT. RAW, WAW, and WAR ALAT
dependencies are allowed within an instruction group and behave as described for
memory dependencies.
The net effect of the dependency restrictions stated above is that a processor may
execute all (or any subset) of the instructions within a legal instruction group
concurrently or serially with the end result being identical. If these dependency
restrictions are not met, the behavior of the program is undefined (see
“Undefined
Behavior” on page 1:44 ).
Exceptions are reported in instruction order. The dependency restrictions apply
independent of the presence or absence of exceptions — that is, restrictions must be
satisfied whether or not an exception occurs within an instruction group. At the point of
exception delivery for a correctly formed instruction group, all prior instructions will
have completed their update of architectural state. All subsequent instructions will not
have updated architectural state. If an instruction group violates a dependency
requirement, then the update of architectural state before and after an exception is not
guaranteed (the fault handler sees an undefined value on the registers involved in a
dependency violation even if the exception occurs between the first and second
instructions in the violation). In the event multiple exceptions occur while executing
instructions from the same instruction group, the exception occurring on the earliest
instruction will be reported.
The instruction sequencing resulting from the rules stated above is termed sequential
execution.