Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 265 / 1898

Volume 2, Part 1: System State and Programming Model 2:17
System State and Programming Model 3
This chapter describes the architectural state visible only to an operating system and
defines system state programming models. It covers the functional descriptions of all
the system state registers, descriptions of individual fields in each register, and their
serialization requirements. The virtual and physical memory management details are
described in
Chapter 4, “Addressing and Protection.” Interruptions are described in
Chapter 5, “Interruptions.”
Note: Unless otherwise noted, references to “interruption” in this chapter refer to
IVA-based interruptions. See
“Interruption Definitions” on page 2:95 .
3.1 Privilege Levels
Four privilege levels, numbered from 0 to 3, are provided to control access to system
instructions, system registers and system memory areas. Level 0 is the most privileged
and level 3 the least privileged. Application instructions and registers can be accessed
at any privilege level. System instructions and registers defined in this chapter can only
be accessed at privilege level 0; otherwise, a Privilege Operation fault is raised. The
processor maintains a Current Privilege Level (CPL) in the cpl field of the Processor
Status Register (PSR). CPL can only be modified by controlled entry and exit points
managed by the operating system. Virtual memory protection mechanisms control
memory accesses based on the Privilege Level (PL) of the virtual page and the CPL.
3.2 Serialization
For all application and system level resources, apart from the control register file, the
processor ensures values written to a register are observed by instructions in
subsequent instruction groups. This is termed
data dependency . For example, writes
to general registers, floating-point and application registers are observed by
subsequent reads of the same register. (See
“Control Registers” on page 2:29 for
control register serialization requirements.) For modifications of application level
resources with side effects, the side effects are ensured by the processor to be
observed by subsequent instruction groups. This is termed
implicit serialization .
Application registers (ARs), with the exception of the Interval Time Counter, the User
Mask, when modified by
sum
,
rum
, and mov to psr.um, and the Current Frame Marker
(CFM), are implicitly serialized. PMD registers have special serialization requirements as
described in
“Generic Performance Counter Registers” on page 2:156 . All other
application-level resources (GRs, FRs, PRs, BRs, IP, CPUID) have no side effects and so
need not be serialized.
To avoid serialization overhead in privileged operating system code, system register
resources are not implicitly serialized. The processor does not ensure modification of
registers with side effects are observed by subsequent instruction groups. For system
register resources other than control registers, the processor ensures data
dependencies are honored (reads see the results of prior writes to the same register).
See Section 3.3.3, “Control Registers” and
Table 3-3 on page 2:29 for control register