Volume 4: Base IA-32 Instruction Reference
4:325
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack
Description
Decrement the stack pointer by 4 (if the current operand-size attribute is 32) and push
the entire contents of the EFLAGS register onto the procedure stack or decrement the
stack pointer by 2 (if the operand-size attribute is 16) push the lower 16 bits of the
EFLAGS register onto the stack. (These instructions reverse the operation of the
POPF/POPFD instructions.)
When copying the entire EFLAGS register to the stack, bits 16 and 17, called the VM
and RF flags, are not copied. Instead, the values for these flags are cleared in the
EFLAGS image stored on the stack.
The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the
same opcode. The PUSHF instruction is intended for use when the operand-size
attribute is 16 and the PUSHFD instruction for when the operand-size attribute is 32.
Some assemblers may force the operand size to 16 when PUSHF is used and to 32
when PUSHFD is used. Others may treat these mnemonics as synonyms
(PUSHF/PUSHFD) and use the current setting of the operand-size attribute to
determine the size of values to be pushed from the stack, regardless of the mnemonic
used.
When the I/O privilege level (IOPL) is less than 3 in virtual-8086 mode, the
PUSHF/PUSHFD instructions causes a general protection exception (#GP). The IOPL is
altered only when executing at privilege level 0. The interrupt flag is altered only when
executing at a level at least as privileged as the IOPL. (Real-address mode is equivalent
to privilege level 0.) If a PUSHF/PUSHFD instruction is executed with insufficient
privilege, an exception does not occur, but the privileged bits do not change.
In the real-address mode, if the ESP or SP register is 1, 3, or 5 when the
PUSHA/PUSHAD instruction is executed, the processor shuts down due to a lack of
stack space. No exception is generated to indicate this condition.
Operation
IF VM=0 (* Not in Virtual-8086 Mode *)
THEN
IF OperandSize = 32
THEN
push(EFLAGS AND 00FCFFFFH);
(* VM and RF EFLAG bits are cleared in image stored on the stack*)
ELSE
push(EFLAGS); (* Lower 16 bits only *)
FI;
ELSE (* In Virtual-8086 Mode *)
IF IOPL=3
THEN
IF OperandSize = 32
Opcode
Instruction
Description
9C
PUSHF
Push EFLAGS
9C
PUSHFD
Push EFLAGS
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...