Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 798 / 1898

2:550 Volume 2, Part 2: Context Management
4.1.1 Preserving General Registers
The Itanium general register file is partitioned into two register sets: GR0-31 are
termed the
static general registers and GR32-127 are termed the stacked general
registers . Typically,
st8.spill
and
ld8.fill
instructions are used to preserve the
static GRs, and the processor’s register stack engine (RSE) automatically preserves the
stacked GRs.
Using the
st8.spill
and
ld8.fill
instructions, the general register value and its NaT
bit are always preserved and restored in unison. However, these instructions do not
save and restore a register’s data speculative state in the Advanced Load Address Table
(ALAT). To maintain the correct ALAT state, software is therefore required to explicitly
invalidate a register’s ALAT entry using the
invala.e
instruction when restoring a
general register. The Itanium calling conventions avoid such explicit ALAT invalidations
by disallowing data speculation to preserved registers (GR4-7) across procedure calls.
Spills and fills of general registers using
st8.spill
and
ld8.fill
cause implicit
collection and restoration of the accompanying NaT bits to/from the User NaT collection
application register (UNAT). The UNAT register needs to be preserved by software
explicitly. The spill and fill instructions derive the UNAT bit index of a spilled/filled NaT
bit from the spill/fill memory address and not from the spilled/filled register index. As a
result, software needs to ensure that the 512-byte alignment offset
1
of the spill/fill
memory address is preserved when a general register is restored. This can be an issue
particularly for user context data structures that may be moved around in memory
(e.g. a
setjmp()
jump buffer).
Unlike the
st8.spill
and
ld8.fill
instructions, the register stack engine (RSE)
preserves not only register values and register NaT bits, but it also manages the
stacked register’s ALAT state by invalidating ALAT that could be reused by software
when the physical register stack wraps. This automatic management of ALAT state
across procedure calls permits compilers to use speculative advanced loads (
ld.sa
) to
perform cross-procedure call control and data speculation in stacked general registers
(GR32-127). Whenever software changes the virtual to physical register mapping of the
stacked registers, the ALAT needs to be invalidated explicitly using the
invala
instruction. Typically this happens during process/thread context switches or in
longjmp()
when the register stack is reloaded with a new BSPSTORE. Refer to
Section 4.5.1.1, “Non-local Control Transfers (setjmp/longjmp)” on page 2:557 .
The RSE collects the NaT bits of the stacked general registers within the RNAT
application register and automatically saves and restores accumulated RNAT collections
to/from fixed locations within the register stack backing store. RNAT collections are
placed on the backing store whenever BSPSTORE bits{8:3} are all one, which results in
one RNAT collection for every 63 registers. When software copies a backing store to a
new location, it is required to maintain the backing store’s 512-byte alignment offset
2
to ensure that the RNAT collections get placed at the proper offset.
1. The specific requirement is that (fill_address mod 512) must be equal to (spill_address mod 512).
2. The specific requirement is that (old_bspstore mod 512) must be equal to (new_bspstore mod 512).