Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 853 / 1898

Volume 2, Part 2: External Interrupt Architecture 2:605
the way out of an uninterruptable code section software is not required to serialize the
setting of PSR.i either, unless it is of interest to software to be able to take interrupts in
the very next instruction group. A code example for this case is given below:
rsm i ;;
// rsm of PSR.i takes effect on the next instruction
// uninterruptable code sequence here
ssm i ;;
// ssm of PSR.i does require data serialization, if we need to ensure
// that external interrupts are enabled at the very next instruction. If
// data serialization is omitted, PSR.i is set to 1 at the latest when
// the next exception is taken.
By avoiding the serialization operations on PSR.i the performance of such
uninterruptable code sections is improved.
10.3.2 IVR Reads and EOI Writes
As described in Section 10.4 , IVR reads return the highest priority, pending, unmasked
vector, and places this vector “in-service.” Additionally, IVR reads have the side-effect
of masking all vectors that have equal or lower priority than one that is returned by the
IVR read. Correspondingly, writes to the EOI register unmask all vectors with equal or
lower priority than the highest priority “in-service” vector. Due to nesting of higher
priority interrupts, it is possible to have multiple vectors in the “in-service” state.
10.3.3 Task Priority Register (TPR)
The Task Priority Register (TPR) provides an additional interrupt masking capability. It
allows software to mask interrupt “priority classes” of 16 vectors each by specifying the
mask priority class in the TPR.mic field. The TPR.mmi field allows masking of all
maskable external interrupts (essentially all but NMI).
An example of TPR use is shown in Section 10.5.2, “TPR and XPTR Usage Example” on
page 2:608 .
10.3.4 External Task Priority Register (XTPR)
The External Task Priority Register (XTPR) is a per-processor resource that can be
provided by external bus logic in some Itanium architecture-based platforms. If
supported by the platform, XTPR can be used by the operating system to redirect
external interrupts to other processors in a multiprocessor system.
The XTPR is updated by performing a 1-byte store to the XTP byte which is located at
an offset of 0x1e0008 in the Processor Interrupt Block (see
Section 5.8.4, “Processor
Interrupt Block” for details). Since the timing of the modification of the XTP register is
not time critical there is no serialization required. Effects of the one byte store
operation are platform specific. Typically, it will generate a transaction on the system
bus identifying it as an XTP register update transaction, and will indicate which
processor generated the transaction as well as the stored data.
An example of XTPR use is included in Section 10.5.2, “TPR and XPTR Usage Example”
on page 2:608 .