Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 172 / 1898

Volume 1, Part 2: Memory Reference 1:161
3.5.6 Minimizing Check Code
Checks of speculative loads can sometimes be combined to reduce code size. The
propagation of NaT bits and NaTVals via speculative instructions can permit a single
check of a speculative result to replace multiple intermediate checks. The code below
demonstrates this optimization potential:
ld4.s r1=[r10] // Speculatively load to r1
ld4.s r2=[r20] // Speculatively load to r2
add r3=r1,r2;; // Add two speculative values
// Other instructions
chk.s r3, imm
21
// Check for NaT bit in r3
st4 [r30]=r1 // Store r1
st4 [r40]=r2 // Store r2
st4 [r50]=r3 // Store r3
Only the result register,
r3
, needs to be checked before stores of any of
r1
,
r2
, or
r3
.
If a NaT bit were set at the time of the control speculative loads of
r1
or
r2
, the NaT bit
would have been propagated to
r3
from
r1
or
r2
via the
add
instruction.
Another way to reduce the amount of check code is to use control flow analysis to avoid
issuing extra
ld.c
or
ld.a
instructions. For example, the compiler can schedule a
single check where it is known to be reached by all copies of the advanced load. The
portion of a flow graph shown in
Figure 3-4 demonstrates where this technique might
be applied.
A single check in the lowermost block shown for all of the advanced loads is correct if
both of these conditions are met:
• The lowermost block post-dominates all of the blocks with advanced loads from
location
addr.
• The lowermost block precedes any uses of the advanced loads from
addr.
Figure 3-4. Using a Single Check for Three Advanced Loads
ld.a
ld.a
ld.a
*p1 =
*p2 = *p3 =
ld.c
Advanced loads from addr
to the same register, R
Stores
Single load check of
register R