Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 332 / 1898

2:84 Volume 2, Part 1: Addressing and Protection
Inter-Processor Interrupt Messages (8-byte stores to a Processor Interrupt Block
address, through a UC memory attribute) are exceptions to the sequential semantics.
IPI's are not ordered with respect to other IPI's directed at the same processor. Further,
fence operations do not enforce ordering between two IPI's. See
Section 5.8.4.2,
“Interrupt and IPI Ordering” on page 2:130 .
Table 4-16 defines the ordering between unordered, release, acquire and fence type
operations to sequential and non-sequential pages. Table 4-16 defines the minimal
ordering requirements; an implementation may enforce more restrictive ordering than
required by the architecture. The actual mechanism for enforcing memory access
ordering is implementation dependent.
Table 4-16 establishes an order between operations on a particular processor. For
operations to cacheable write-back memory the order established by these rules is
observed by all observers in the coherence domain.
For example, when this sequence is executed on a processor:
st [a]
st.rel [b]
and a second processor executes this sequence:
ld.acq [b]
ld [a]
if the second processor observes the store to [b], it will also observe the store to [a].
Unless an ordering constraint from Table 4-16 prevents a memory read
1
from becoming
visible, the read may be satisfied with values found in a store buffer (or any logically
equivalent structure). These values need not be globally visible even when the
operation that created the value was a
st.rel
. This local bypassing behavior may make
Table 4-16. Ordering Semantics
Second Operation
First Operation Fence
Non-sequential Sequential
a
a. Except for IPI.
Acquire Release Unordered Acquire Release Unordered
Fence O O O O O O O
Non-sequential Acquire O O O O O O O
Release O – O – – O –
Unordered O – O – – O –
Sequential
a
Acquire O O O O OS OS OS
Release O – O – S OS S
Unordered O – O
b
b. “O” indicates that the first and second operation become visible in program order.
–
c
c. A dash indicates no ordering is implied.
S
d
d. “S” indicates that the first and the second operation reach a peripheral domain in program order.
OS
e
e. “OS” implies that both “O” and “S” ordering relations apply.
S
1. This includes all types of loads (
ld
and
ld.acq
), and RSE memory reads. Note, however, that the
read operation of semaphores cannot be satisfied with values found in a store buffer.