Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 774 / 1898

2:526 Volume 2, Part 2: MP Coherence and Synchronization
2.3 Where the Intel
®
Itanium
®
Architecture Requires
Explicit Synchronization
The Itanium architecture requires a memory synchronization (
sync.i
) and a memory
fence (
mf
) during a context switch to ensure that all memory operations prior to the
context switch are made visible before the context changes. Without this requirement,
the ordering constraints may be violated if the process migrates to a different
processor. For example, consider the example shown in
Figure 2-3 .
.
In this example, Processor #1 may make the unordered store visible to the coherence
domain before Processor #0 makes the acquire load visible. This violates the ordering
constraints. Executing a memory fence during the context switch handler ensures that
this violation can not occur.
See Section 4.5, “Context Switching” on page 2:557 on context management in a
processor based on the Itanium architecture.
Interruptions do not affect memory ordering. On entry to an interrupt handler, memory
operations from the interrupted program may still be in-flight and not yet visible to
other processors in the coherence domain. A handler that expects that all memory
operations that precede the interruption to be visible must enforce this requirement by
executing a memory fence at the beginning of the handler.
2.4 Synchronization Code Examples
There are many synchronization primitives that software uses in multiprocessor or
multi-threaded environments to coordinate the activities of different code streams. In
this section, we present several typical examples to illustrate how some common
constructs translate to the Itanium instruction set. In addition, the discussions identify
special considerations with various implementations.
The examples use the syntax “[
foo
]” to indicate the memory location that holds the
variable
foo
. Actual Itanium architecture-based assembly language would first move
the address of
foo
into a register and then use this register as an operand to a memory
access instruction. The alternate syntax is chosen to simplify and clarify the examples.
Figure 2-3. Why a Fence During Context Switches is Required in the Intel
®
Itanium
®
Architecture
// Process A begins executing on Processor #0...
ld.acq r1 = [x] // load executes on processor #0
// 1) Context switch occurs
// 2) O/S migrates Process A from Processor #0 to Processor #1
// 3) Process A resumes at the instruction following the ld.acq
st [y] = r2 // store executes on processor #1