Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 1713 / 1898

Volume 4: IA-32 Intel
®
MMX™ Technology Instruction Reference 4:411
PADDB/PADDW/PADDD—Packed Add (continued)
Note that like the integer ADD instruction, the PADDB, PADDW, and PADDD instructions
can operate on either unsigned or signed (two's complement notation) packed integers.
Unlike the integer instructions, none of the MMX technology instructions affect the
EFLAGS register. With MMX technology instructions, there are no carry or overflow flags
to indicate when overflow has occurred, so the software must control the range of
values or else use the “with saturation” MMX technology instructions.
Operation
IF instruction is PADDB
THEN
DEST(7..0)

DEST(7..0) + SRC(7..0);
DEST(15..8)

DEST(15..8) + SRC(15..8);
DEST(23..16)

DEST(23..16)+ SRC(23..16);
DEST(31..24)

DEST(31..24) + SRC(31..24);
DEST(39..32)

DEST(39..32) + SRC(39..32);
DEST(47..40)

DEST(47..40)+ SRC(47..40);
DEST(55..48)

DEST(55..48) + SRC(55..48);
DEST(63..56)

DEST(63..56) + SRC(63..56);
ELSEIF instruction is PADDW
THEN
DEST(15..0)

DEST(15..0) + SRC(15..0);
DEST(31..16)

DEST(31..16
)
+ SRC(31..16);
DEST(47..32)

DEST(47..32
)
+ SRC(47..32);
DEST(63..48)

DEST(63..48) + SRC(63..48);
ELSE (* instruction is PADDD *)
DEST(31..0)

DEST(31..0) + SRC(31..0);
DEST(63..32)

DEST(63..32) + SRC(63..32);
FI;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault