Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 327 / 1898

Volume 2, Part 1: Addressing and Protection 2:79
become flushed and made visible prior to itself becoming visible. Even though IA-32
stores and loads are ordered, the write-coalesced data is not flushed unless the IA-32
stores or loads are to uncached memory types.
The Flush Cache (
fc
,
fc.i
) instruction flushes all write-coalesced data whose address
is within at least 32 bytes of the 32-byte aligned address specified by the Flush Cache
(
fc
,
fc.i
) instruction, forcing the data to become visible. The Flush Cache (
fc
,
fc.i
)
instruction may also flush additional write-coalesced data. The Flush Write buffers (
fwb
)
instruction is a “hint” to the processor to expedite flushing (visibility) of any pending
stores held in the coalescing buffer(s), without regard to address.
No indication is given when the flushing of the stores is completed. An
fwb
instruction
does not ensure ordering of coalesced stores, since later stores may be flushed before
prior stores. To ensure prior coalesced stores are made visible before later stores,
software must issue a release operation between stores.
The processor may at any time flush coalesced stores in any order before explicitly
requested to do so by software.
Coalesced pages are not ensured to be coherent with other processors’ coalescing
buffers or caches, or with the local processor’s caches. Loads to coalesced memory
pages by a processor see the results of all prior stores by the same processor to the
same coalesced memory page. Memory references made by the coalescing buffer (e.g.,
buffer flushes) have an unordered non-sequential memory ordering attribute.
See
“Sequentiality Attribute and Ordering” on page 2:82.
Data that has been read or prefetched into a coalescing buffer prior to execution of an
Itanium acquire or fence type instruction is invalidated by the acquire or fence
instruction. (See
Table 4-15 for a list of acquire and fence instructions.)
4.4.6 Speculation Attributes
For present pages (TLB.p=1) which are marked with a speculative or a NaTPage
memory attribute, the processor may prefetch instructions (including IA-32), perform
address generation and perform load accesses (including IA-32) without resolving prior
control dependencies, including predicates, branches and interruptions. A page should
only be marked speculative if accesses to that page have no side-effects. For example,
many memory-mapped I/O devices have side-effects associated with reads and should
be marked non-speculative. If a page is marked speculative, a processor can read any
location in the page at any time independent of a programmer’s intentions or control
flow changes. As a result, software is required, at all times, to maintain valid page table
attributes for the ppn, ps and ma fields of all present translations whose memory
attribute is speculative or NaTPage. (For example, software should not insert into the
TLB, nor create in the VHPT, mappings whose memory attribute is WB, WC or NaTPage
unless the entire corresponding physical address range is populated. Placing such
mappings in the VHPT or inserting such mappings in the TLB could result in machine
check aborts.) High-performance operation is only attainable on speculative pages. The
speculative attribute is a hint; a processor may behave non-speculatively.