Volume 1, Part 1: Introduction to the Intel
®
Itanium
®
Architecture
1:17
the compiler uses control speculation, it leaves a check operation at the original
location. The check verifies whether an exception has occurred and if so it branches to
recovery code. The code sequence above now translates into:
/* off critical path */
sload(ld_addr1,target1)
sload(ld_addr2,target2)
/* other operations including uses of target1/target2 */
if (a>b) scheck(target1,recovery_addr1)
else scheck(target2, recovery_addr2)
2.6.2
Data Speculation
Data speculation is the execution of a memory load prior to a store that preceded it and
that may potentially alias with it. Data speculative loads are also referred to as
“advanced loads.” Consider the code sequence below:
store(st_addr,data)
load(ld_addr,target)
use(target)
The process of determining at compile time the relationship between memory
addresses is called disambiguation. In the example above, if
ld_addr
and
st_addr
cannot be disambiguated, and if the load were to be performed prior to the store, then
the load would be data speculative with respect to the store. If memory addresses
overlap during execution, a data-speculative load issued before the store might return a
different value than a regular load issued after the store. Therefore analogous to
control speculation, when the compiler data speculates a load, it leaves a check
instruction at the original location of the load. The check verifies whether an overlap
has occurred and if so it branches to recovery code. The code sequence above now
translates into:
/* off critical path */
aload(ld_addr,target)
/* other operations including uses of target */
store(st_addr,data)
acheck(target,recovery_addr)
use(target)
2.6.3
Predication
Predication is the conditional execution of instructions. Conditional execution is
implemented through branches in traditional architectures. The Itanium architecture
implements this function through the use of predicated instructions. Predication
removes branches used for conditional execution resulting in larger basic blocks and the
elimination of associated mispredict penalties.
To illustrate, an unpredicated instruction
r1 = r2 + r3
when predicated, would be of the form
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...