Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 863 / 1898

Volume 2, Part 2: I/O Architecture 2:615
I/O Architecture 11
I/O devices can be accessed from Itanium architecture-based programs using regular
loads and stores to uncacheable space. While cacheable Itanium memory references
may be reordered by the processor, uncacheable I/O references are always presented
to the platform in program order. This “sequentiality” of uncacheable references is
discussed in
Section 2.2.2, “Memory Attributes” on page 2:524 and in more detail in
Section 4.4.7, “Sequentiality Attribute and Ordering” on page 2:82 .
Additionally, uncacheable memory pages are defined to be “non-speculative” which
causes all data and control speculative loads to uncacheable pages to defer. Control
speculative loads to uncacheable memory return a NaT/NaTVal to their target register.
Data speculative loads to uncacheable memory return zero to their target register. For
details, refer to
Section 4.4.6, “Speculation Attributes” on page 2:79 .
When configuring chipset registers or setting up device registers, it is sometimes
required to know when a memory transaction has been completed. Completion means
the processor received acknowledgment that the transaction finished successfully in the
platform, and that all its side-effects have occurred and will be visible to the next
memory operation (issued by the same processor). To ensure completion of prior
accesses on the platform, the Itanium architecture provides the
mf.a
instruction. Unlike
the
mf
instruction that waits for visibility of prior operations, the
mf.a
waits for
completion of prior operations on the platform. More details in Section 11.1 .
To fully leverage the large set of existing platform infrastructure and I/O devices, the
architecture also supports the IA-32 platform I/O port space. The Itanium instruction
set does not provide IN and OUT instructions, but they can be emulated. The I/O port
space can be mapped into user-space, and IA-32 applications can use IN and OUT
instructions to directly communicate with the I/O port space. More details in
Section 11.2 .
The Itanium architecture provides a high-performance, high-bandwidth uncacheable
memory attribute that supports write-coalescing. This allows the processor to burst
writes to uncacheable locations at much higher bandwidth. The Itanium architecture
does
not guarantee the FIFO delivery of write-coalescing stores. More details in
Section 4.4.5, “Coalescing Attribute” on page 2:78 .
11.1 Memory Acceptance Fence (mf.a)
An
mf
instruction ensures that all cache coherent agents have observed all prior
memory operations made by the processor issuing the
mf
. However, it does not ensure
that those operations have completed, in the Itanium architecture parlance it does not
ensure that they have been “accepted” by the external platform. For instance, a load
may have been made visible to all processors by snooping their caches, but the data
return may still be in progress. Such a load would be visible, but not complete.