2:330
Volume 2, Part 1: Processor Abstraction Layer
a_to_int_cr
2
Enable the interruption control register (CR16-27) write optimization. See
Section 11.7.4.2.3, “Interruption Control Register Write Optimization” on
page 2:341
for details.
a_from_psr
3
Enable the processor status register read optimization. See
Section 11.7.4.2.4, “MOV-from-PSR Optimization” on page 2:341
for details.
a_from_cpuid
4
Enable the CPUID read optimization. See
“MOV-from-CPUID Optimization” on page 2:342
for details.
a_cover
5
Enable the
cover
instruction optimization. See
for details.
a_bsw
6
Enable the
bsw
instruction optimization. See
Section 11.7.4.2.7, “Bank Switch
for details.
a_all_probes
7
Enable virtualization of probe instructions. See
Instruction Virtualization” on page 2:344
for details.
a_select_probes
8
a_tf
9
Enable the test feature optimization. See
Section 11.7.4.2.9, “Test Feature
for details.
a_ic_um
10
Enable the interruption collection and user mask optimization. See
Section 11.7.4.2.10, “Interruption Collection and User Mask Optimization” on
page 2:345
for details.
Reserved
63:11
Reserved
Figure 11-14. Virtualization Disable Control (
vdc
)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
Disable Controls
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
Table 11-20. Virtualization Disable Control (
vdc
) Fields
Field
Bits
Description
d_vmsw
0
Disable
vmsw
instruction – If 1, disables
vmsw
instruction on the logical pro-
cessor. Execution of the
vmsw
instruction, independent of the state of
PSR.vm, will cause a virtualization intercept.
d_extint
1
Disable external interrupt control register virtualization – If 1, accesses
(reads/writes) of the external interrupt control registers (CR65-71) are not vir-
tualized. Code running with PSR.vm==1 can read and write the external inter-
rupt control registers of the logical processor directly and without handling off
to the VMM. See
Section 11.7.4.3.2, “Disable External Interrupt Control Reg-
ister Virtualization” on page 2:347
for details.
d_ibr_dbr
2
Disable breakpoint register virtualization – If 1, accesses (reads/writes) of the
data and instruction breakpoint registers (IBR/DBR) are not virtualized. Code
running with PSR.vm==1 can read and write the data/instruction breakpoint
registers of the logical processor directly and without handling off to the VMM.
If 0, accesses of the breakpoint registers with PSR.vm==1 result in virtualiza-
tion intercepts.
d_pmc
3
Disable PMC virtualization – If 1, accesses (reads/writes) of the performance
monitor configuration registers (PMCs) are not virtualized. Code running with
PSR.vm==1 can read and write the performance monitor configuration regis-
ters of the logical processor directly and without handling off to the VMM.
If 0, accesses of the performance counter configuration registers with
PSR.vm==1 result in virtualization intercepts.
Table 11-19. Virtualization Acceleration Control (
vac
) Fields (Continued)
Field
Bit
Description
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...