Volume 2, Part 1: Processor Abstraction Layer
2:347
11.7.4.3.1 Disable VMSW Instruction
The VMSW instruction disable is controlled by the d_vmsw bit in the Virtualization
Disable Control (
vdc
) field in the VPD. When this control is set to 1, the
vmsw
instruction
is disabled on the logical processor. Execution of the
vmsw
instruction, independent of
the state of PSR.vm, results in a virtualization intercept.
If this control is set to 0, the
vmsw
instruction can be executed by both the VMM and
guest without virtualization intercepts, if PSR.it is 1 and the
vmsw
instruction is
executed on a page with access rights of 7.
11.7.4.3.2 Disable External Interrupt Control Register Virtualization
The external interrupt control register virtualization disable is controlled by the d_extint
bit in the Virtualization Disable Control (
vdc
) field in the VPD. When this control is set to
1, the external interrupt control registers (CR65-71) are not virtualized, and code
running with PSR.vm==1 can read and write these resources directly without any
intercepts to the VMM.
If this control is set to 0, accesses (reads/writes) to the external interruption control
registers with PSR.vm==1 result in virtualization intercepts.
Note:
This field cannot be enabled together with the a_int virtualization acceleration
control (vac) described in
Section 11.7.4.2.1, “Virtual External Interrupt Opti-
. If this control is enabled together with the a_int con-
trol, an error will be returned during PAL_VP_CREATE and PAL_VP_REGISTER.
See
Section 11.7.4.4, “Virtualization Optimization Combinations” on
for details.
11.7.4.3.3 Disable Breakpoint Register Virtualization
The breakpoint register virtualization disable is controlled by the d_ibr_dbr bit in the
Virtualization Disable Control (
vdc
) field in the VPD. When this control is set to 1,
accesses (reads/writes) to the data and instruction breakpoint registers (DBR/IBR) are
not virtualized, and code running with PSR.vm==1 can read and write these resources
directly without any intercepts to the VMM.
If this control is set to 0, accesses (reads/writes) to the breakpoint registers with
PSR.vm==1 result in virtualization intercepts.
Disable ITM Virtualization
d_itm
Disable PSR Interrupt-bit Virtualization
d_psr_i
a. The Virtualization Disable Control (
vdc
) field resides in the Virtual Processor Descriptor (VPD), see
Section 11.7.1, “Virtual Processor Descriptor (VPD)” on page 2:325
for details.
Table 11-46. Virtualization Disables Summary (Continued)
Disable
Virtualization
Disable Control
(
vdc
)
a
Description
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...