Volume 2, Part 1: Processor Abstraction Layer
2:349
11.7.4.4
Virtualization Optimization Combinations
describes the supported combinations of virtualization accelerations and
disables.
11.7.4.4.1 Virtual External Interrupt Optimization and Interruption Collection
and User Mask Optimization
The execution of
rsm
and
ssm
instructions with PSR.vm==1 is affected by both of these
optimizations:
• Virtual External Interrupt Optimization (a_int), described in
“Virtual External Interrupt Optimization”
, and
• Interruption Collection and User Mask Optimization (a_ic_um), described in
11.7.4.2.10, “Interruption Collection and User Mask Optimization”
Software can enable or disable both optimizations together, or enable each optimization
independently.
When both optimizations are enabled and PSR.vm==1,
rsm
and
ssm
instructions with a
mask targeting any fields in i, ic and user mask will not be intercepted to the VMM,
unless a fault condition is detected, The i and ic fields in vpsr and user mask in PSR will
be updated with the new value.
When PSR.vm==1,
rsm
and
ssm
instructions with a mask targeting any fields other
than i, ic and user mask fields will result in virtualization intercepts independent of
whether these two optimizations are enabled or not.
11.7.4.5
Virtualization Synchronizations
When certain virtualization accelerations described in
Section 11.7.4.2, “Virtualization
are enabled, processor implementations can provide
implementation-specific control resources to enhance the performance of virtual
processors. Two PAL services are provided to synchronize the implementation-specific
control resources and the resources in the VPD. There are two types of
synchronizations:
Table 11-47.Supported Virtualization Optimization Combinations
d_vmsw
d_extint
d_ibr_dbr
d_pmc
d_to_pmd
d_itm
d_psr_i
a_int
o
a
a. “o” indicates the corresponding virtualization acceleration and disable can be enabled together.
x
b
b. “x” indicates the corresponding virtualization acceleration and disable cannot be enabled together.
o
o
o
o
x
a_from_int_cr
o
o
o
o
o
o
o
a_to_int_cr
o
o
o
o
o
o
o
a_from_psr
o
o
o
o
o
o
x
a_from_cpuid
o
o
o
o
o
o
o
a_cover
o
o
o
o
o
o
o
a_bsw
o
o
o
o
o
o
x
a_all_probes
o
o
o
o
o
o
o
a_select_probes
o
o
o
o
o
o
o
a_tf
o
o
o
o
o
o
o
a_ic_um
o
o
o
o
o
o
o
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...
