Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 97 / 1898

1:86 Volume 1, Part 1: Floating-point Programming Model
Real numbers reside in 82-bit floating-point registers in a three-field binary format (see
Figure 5-1 ). The three fields are:
• The 64-bit significand field, b
63
. b
62
b
61 ..
b
1
b
0,
contains the number's significant
digits. This field is composed of an explicit integer bit (significand{63}), and 63 bits
of fraction (significand{62:0}).
• The 17-bit exponent field locates the binary point within or beyond the significant
digits (i.e., it determines the number's magnitude). The exponent field is biased by
65535 (0xFFFF). An exponent field of all ones is used to encode the special values
for IEEE signed infinity and NaNs. An exponent field of all zeros and a significand
field of all zeros is used to encode the special values for IEEE signed zeros. An
exponent field of all zeros and a non-zero significand field encodes the
double-extended real denormals and double-extended real pseudo-denormals.
• The 1-bit sign field indicates whether the number is positive (sign=0) or negative
(sign=1).
The value of a finite floating-point number, encoded with non-zero exponent field, can
be calculated using the expression:
The value of a finite floating-point number, encoded with zero exponent field, can be
calculated using the expression:
Integers (64-bit signed/unsigned) and Parallel FP numbers reside in the 64-bit
significand field. In their canonical form, the exponent field is set to 0x1003E (biased
63) and the sign field is set to 0.
5.1.3 Representation of Values in Floating-point Registers
The floating-point register encodings are grouped into classes and subclasses and listed
below in
Table 5-2 (shaded encodings are unsupported). The last two table entries
contain the values of the constant floating-point registers, FR 0 and FR 1. The constant
value in FR 1 does not change for the parallel single precision instructions or for the
integer multiply accumulate instruction.
Figure 5-1. Floating-point Register Format
81 80 64 63 0
sign exponent significand (with explicit integer bit)
1 17 64
(-1)
(sign)
* 2
(exponent - 65535)
* (significand{63}.significand{62:0}
2
)
(-1)
(sign)
* 2
(-16382)
* (significand{63}.significand{62:0}
2
)
Table 5-2. Floating-point Register Encodings
Class or Subclass
Sign
(1 bit)
Biased
Exponent
(17-bits)
Significand
i.bb...bb
(Explicit Integer Bit is Shown)
(64-bits)
NaNs 0/1 0x1FFFF 1.000...01 through 1.111...11
Quiet NaNs 0/1 0x1FFFF 1.100...00 through 1.111...11
Quiet NaN Indefinite
a
1 0x1FFFF 1.100...00
Signaling NaNs 0/1 0x1FFFF 1.000...01 through 1.011...11
Infinity 0/1 0x1FFFF 1.000...00