Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 411 / 1898

Volume 2, Part 1: Debugging and Performance Monitoring 2:163
follow the implementation-independent overflow interrupt service routine outlined in
Figure 7-7 . Use of alternate context-switch sequences may be incompatible with future
implementations.
If the outgoing context has an interrupt pending but has not yet invoked the
performance monitor interrupt service routine, the interrupt may be delivered to the
incoming context even if it is a non-monitored process. The interrupt service routine
can recognize this kind of bogus interrupt by noticing that either: the freeze bit is zero
or the context is not being monitored.
7.2.4.2 Performance Monitor Context Switch
The context switch routine described in Figure 7-8 defines the
implementation-independent context switching of Itanium performance monitors. Using
bit masks provided by PAL (PAL
PMCmask
, PAL
PMDmask
) the routine can generically
save/restore the contents of all implementation-specific performance monitoring
registers. If the outgoing context is monitored, then all PMC and PMD registers whose
mask bit is set are preserved by software. But if the outgoing context is monitored and
the context switch routine determines that the outgoing context has a pending
performance monitor interrupt (by reading the freeze bit with the knowledge that it was
not generated by software) then software also preserves the outgoing context's
overflow status registers (PMC[0]..PMC[3]) before all PMC and PMD registers whose
mask bit is set. Here, it is explicitly assumed that software tracks monitored processes
and can determine whether a process is monitored prior to reading the freeze bit. The
context switch handler then restores the performance monitor freeze bit which resets
event collection for the new context. Sometime into the incoming (possibly
unmonitored) context, the performance overflow interrupt service routine will run, but
by looking at the status of the freeze bit software can determine whether this interrupt
can be ignored (for details refer to
Section 7.2.4.1 ).
Figure 7-7. Performance Monitor Interrupt Service Routine
(Implementation Independent)
//Assumes PSR.up and PSR.pp are switched to zero together
if ((PMC[0].fr==1) && (PSR.up == 1) || (PSR.pp == 1)){
// freeze bit is set. Search for interrupt.
for (i=0; i< 4; i++) {
if (PMC[i] != 0) {
startbit = (i==0) ? 4 : 0;
for (j=startbit; j < 64 ; j++) {
if (PMC[i]{j}) {
counter_id = 64*i + j;
if (counter_id > PAL_GENERIC_PMCPMD_PAIRS) {
Implementation_Specific_Update(counter_id);
}
else { // Generic PMC/PMD counter
if (PMC[counter_id].oi)
ovflcount[counter_id] += 1;
}
}
} // scan overflow bits
}
}
}
// Either ignore bogus interrupt or clear PMC[3]..PMC[1]
for (i=3; i>=1; i--) { PMC[i] = 0; }
rfi