Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 272 / 1898

2:24 Volume 2, Part 1: System State and Programming Model
The system mask, PSR{23:0}, can be set and cleared by the Set System Mask (
ssm
)
and Reset System Mask (
rsm
) instructions. Software must issue the appropriate
serialization operation before dependent instructions. The system mask instructions are
privileged.
The lower half of the PSR, PSR{31:0}, can be written with the Move to Lower PSR (
mov
psr.l=
) instruction. Software must issue the appropriate serialization operation before
dependent instructions. The Move to Lower PSR instruction is privileged.
The PSR can be read with the Move from PSR (
mov =psr
) instruction. Only PSR{36:35}
and PSR{31:0} are written to the target register by Move from PSR. PSR{63:37} and
PSR{34:32} can only be read after an interruption by reading the state in IPSR. The
entire PSR is updated from IPSR by the Return from Interruption (
rfi
) instruction. An
rfi
also implicitly serializes the PSR. Both Move from PSR and Return from Interruption
are privileged.
Table 3-2. Processor Status Register Fields
Field Bits Description
Interruption
State
Serialization
Required
User Mask = PSR{5:0}
rv
0 reserved
be 1 Big-Endian – When 1, data memory references are
big-endian. When 0, data memory references are little
endian. This bit is ignored for IA-32 data references,
which are always performed little-endian. Instruction
fetches are always performed little endian. DCR.be data
a
up 2 User Performance monitor enable – When 1,
performance monitors configured as user monitors are
enabled to count events (including IA-32). When 0, user
configured monitors are disabled. See
“Performance
Monitoring” on page 2:155 for details.
unchanged data
a
inst
b
ac 3 Alignment Check – When 1, all unaligned data memory
references result in an Unaligned Data Reference fault.
When 0, unaligned data memory references may or
may not result in a Unaligned Data Reference fault. See
“Memory Datum Alignment and Atomicity” on page 2:93
for details. Unaligned semaphore references also result
in a Unaligned Data Reference fault, regardless of the
state of PSR.ac. For IA-32 instructions, if PSR.ac is 1
an unaligned IA-32 data memory reference raises an
IA_32_Exception(AlignmentCheck) fault. When 0,
additional IA-32 control bits as defined in Section
10.6.7, “Memory Alignment” also generate alignment
checks.
0 data
a
mfl 4 Lower (f2 .. f31) floating-point registers written – This bit
is set to one when an Intel Itanium instruction
completes that uses register f2..f31 as a target register.
This bit is sticky and only cleared by an explicit write of
the user mask. When leaving the IA-32 instruction set,
PSR.mfl is set to 1 if PSR.dfl is 0, otherwise PSR.mfl is
unmodified. unchanged data
a