Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 403 / 1898

Volume 2, Part 1: Debugging and Performance Monitoring 2:155
• The
cmp8xchg16
operands are treated as 16-byte datums for both read and write
breakpoint matching, even though this instruction only reads 8 bytes.
Address breakpoint Data Debug faults are not reported for the Flush Cache (
fc
,
fc.i
),
regular_form
probe
, non-faulting
lfetch
, insert TLB (
itc
,
itr
), purge TLB (
ptc
,
ptr
),
or translation access (
thash
,
ttag
,
tak
,
tpa
) instructions. Accesses by the RSE to a
debug region are checked, but the Data Debug fault is not reported until a subsequent
alloc
,
br.ret
,
rfi
,
loadrs
, or
flushrs
which requires that the faulting load or store
actually occur.
The range of addresses detected by the DBR and IBR registers for IA-32 memory
references is defined as:
• Instruction memory references where the first byte of the IA-32 instruction match
the IBR address and mask fields results in an IA_32_Exception(Debug) fault.
Subsequent bytes of a multiple byte IA-32 instruction are not compared against the
IBR registers for breakpoints. The upper 32-bits of the IBR addr field must be zero
to detect IA-32 instruction memory references.
• IA-32 single or multi-byte data memory references that access any memory byte
specified by the DBR address and mask fields results in an
IA_32_Exception(Debug) trap regardless of datum size and alignment. The
processor ensures that all data breakpoint traps are precisely reported. Data
breakpoint traps are reported if and only if any byte in the IA-32 data memory
reference matches the DBR address and mask fields. No spurious data breakpoint
events are generated for IA-32 data memory operands that are unaligned, nor are
breakpoints reported if no bytes of the operand lie within the address range
specified by the DBR address and mask fields.
7.2 Performance Monitoring
Performance monitors allow processor events to be monitored by programmable
counters or give an external notification (such as a pin or transaction) on the
occurrence of an event. Monitors are useful for tuning application, operating system
and system performance. Two sets of performance monitor registers are defined.
Performance Monitor Configuration (PMC) registers are used to control the monitors.
Performance Monitor Data (PMD) Registers either provide data values from the
monitors, or hold data values used by the PMU. The performance monitors can record
performance values from either the IA-32 or Itanium instruction set.
As shown in Figure 7-3 , all processor implementations provide at least four
performance counters (PMC/PMD[4]..PMC/PMD[7] pairs), and four performance
counter overflow status registers (PMC[0]..PMC[3]). Performance monitors are also
controlled by bits in the processor status register (PSR), the default control register
(DCR) and the performance monitor vector register (PMV). Processor implementations
may provide additional implementation-dependent PMC and PMD registers to increase
the number of “generic” performance counters (PMC/PMD pairs). The remainder of the
PMC and PMD register set is implementation dependent.
Event collection for implementation-dependent performance monitors is not specified
by the architecture. Enabling and disabling functions are implementation dependent.
For details, consult processor-specific documentation.