Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Manual

Page: 401 / 1898

Volume 2, Part 1: Debugging and Performance Monitoring 2:153
Four privileged instructions, defined in Table 7-2 , allow access to the debug registers.
Register access is indirect, where the debug register number is determined by the
contents of a general register. DBR/IBR registers can only be accessed at privilege level
0, otherwise a Privileged Operation fault is raised.
Table 7-1. Debug Breakpoint Register Fields (DBR/IBR)
Field Bits Description
addr 63:0 Match Address – 64-bit virtual or physical breakpoint address. Addresses are interpreted as
either virtual or physical based on PSR.dt, PSR.it or PSR.rt. Data breakpoint addresses trap
on load, store, semaphore, and mandatory RSE memory references. For Intel Itanium
instruction set references, IBR.addr{3:0} is ignored in the address match. For IA-32
instruction references, IBR.addr{31:0} are used in the match and IBR.addr{63:32} must be
zero to match. All 64 bits are implemented on all processors regardless of the number of
implemented address bits.
mask 55:0 Address Mask – determines which address bits in the corresponding address register are
compared in determining a breakpoint match. Address bits whose corresponding mask bits
are 1, must match for the breakpoint to be signaled, otherwise the address bit is ignored.
Address bits{63:56} for which there are no corresponding mask bits are always compared.
For IA-32 instruction references, IBR.mask{55:32} are ignored. All 56 bits are implemented
on all processors regardless of the number of implemented address bits.
plm 59:56 Privilege Level Mask – enables data breakpoint matching at the specified privilege level.
Each bit corresponds to one of the four privilege levels, with bit 56 corresponding to privilege
level 0, bit 57 with privilege level 1, etc. A value of 1 indicates that the debug match is
enabled at that privilege level.
w 62 Write match enable – When DBR.w is 1, any non-nullified mandatory RSE store, IA-32 or
Intel Itanium store, semaphore, probe.w.fault or probe.rw.fault to an address matching the
corresponding address register causes a breakpoint.
r 63 Read match enable – When DBR.r is 1, any non-nullified IA-32 or Intel Itanium load,
mandatory RSE load, semaphore, lfetch.fault, probe.r.fault or probe.rw.fault to an address
matching the corresponding address register causes a breakpoint. When DBR.r is 1, a VHPT
access that matches the DBR (except those for a
tak
instruction) will cause an
Instruction/Data TLB Miss fault. If DBR.r and DBR.w are both 0, that data breakpoint register
is disabled.
x 63 Execute match enable – When IBR.x is 1, execution of an IA-32 instruction or Intel Itanium
instruction in a bundle at an address matching the corresponding address register causes a
breakpoint. If IBR.x is 0, that instruction breakpoint register is disabled. Instruction
breakpoints are reported even if the qualifying predicate is false.
ig 62:60 Ignored
Table 7-2. Debug Instructions
Mnemonic Description Operation
Instr
Type
Serialization
Required
mov dbr[ r
3
] = r
2
Move to data breakpoint
register DBR[GR[ r
3
]]

GR[ r
2
] M data
mov r
1
= dbr[ r
3
] Move from data breakpoint
register GR[ r
1
]

DBR[GR[ r
3
]] M none
mov ibr[ r
3
] = r
2
Move to instruction
breakpoint register IBR[GR[ r
3
]]

GR[ r
2
] M inst
mov r
1
= ibr[ r
3
] Move from instruction
breakpoint register GR[ r
1
]

IBR[GR[ r
3
]] M none
break imm Breakpoint Instruction fault if (PSR.ic) IIM

imm
fault(Breakpoint_Instruction)
B/I/M none