2:54
Volume 2, Part 1: Addressing and Protection
• The GR[r] value is checked when a TLB insert instruction is executed, and if
reserved fields or reserved encodings are used, a Reserved Register/Field fault is
raised on the TLB insert instruction. If GR[r]{0} is zero (not-present Translation
Insertion Format), the rest of GR[r] is ignored.
• The RR[vrn] value is checked when a mov to RR instruction is executed, and if
reserved fields or reserved encodings are used, a Reserved Register/Field fault is
raised on the mov to RR instruction.
• The ITIR value is checked either when a mov to ITIR instruction is executed, or
when a TLB insert instruction is executed, depending on the processor
implementation. If reserved fields or reserved encodings are used, a Reserved
Register/Field fault is raised on the mov to ITIR or TLB insert instruction. In
implementations where ITIR is checked on a TLB insert instruction, ITIR{63:32}
and ITIR{31:8} may be ignored if GR[r]{0} is zero (not-present Translation
Insertion Format).
• The IFA value is checked either when a mov to IFA instruction is executed, or when
a TLB insert instruction is executed, depending on the processor implementation. If
an unimplemented virtual address is used, an Unimplemented Data Address fault is
raised on the mov to IFA or TLB insert instruction.
Software must issue an instruction serialization operation to ensure installs into the
ITLB are observed by dependent instruction fetches and a data serialization operation
to ensure installs into the DTLB are observed by dependent memory data references.
describes all the translation interface fields.
Figure 4-5.
Translation Insertion Format
63
53 52 51 50 49
32 31
12 11
9
8
7
6 5 4
2 1 0
GR[
r
]
ig
ed
ci
ppn
ar
pl
d a
ma
ci p
ITIR
rv/ci
key
ps
rv/ci
IFA
vpn
ig
RR[vrn]
rv
rid
ig
rv ig
Table 4-3.
Translation Interface Fields
TLB
Field
Source
Field
Description
ci
GR[
r
]{1,51:50}
Checked on Insert – Checked on a TLB insert instruction. If reserved fields or
encodings are used, a Reserved Register/Field fault is raised on the TLB
insert instruction.
rv/ci
ITIR{1:0,63:32}
Reserved/Checked on Insert – Depending on implementation, may be
reserved (checked on a mov to ITIR instruction) or checked on a TLB insert
instruction. If reserved fields or encodings are used, a Reserved
Register/Field fault is raised on the mov to ITIR or TLB insert instruction. In
implementations where ITIR is checked on a TLB insert instruction,
ITIR{63:32} may be ignored if GR[r]{0} is zero (not-present Translation
Insertion Format).
rv
RR[vrn]{1,63:32}
Reserved – Checked on a mov to RR instruction. If reserved fields or
encodings are used, a Reserved Register/Field fault is raised on the mov to
RR instruction.
Summary of Contents for ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Page 1: ......
Page 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Page 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Page 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Page 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Page 230: ......
Page 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Page 380: ...2 132 Volume 2 Part 1 Interruptions ...
Page 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Page 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Page 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Page 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Page 808: ...2 560 Volume 2 Part 2 Context Management ...
Page 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Page 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Page 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Page 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Page 891: ......
Page 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Page 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Page 1296: ......
Page 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Page 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Page 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Page 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Page 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Page 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...