Rev. 1.0, 02/00, page 342 of 1141
16.7
Precautions when Using Timer X1
Pay great attention to the fact that the following competitions and operations occur during
operation of timer X1.
16.7.1
Competition between Writing and Clearing with the FRC
When a counter clearing signal is issued under the T2 state where the FRC is under the writing
cycle, writing into the FRC will not be effected and the priority will be given to clearing of the
FRC.
Figure 16.13 shows the timing chart.
Address
FRC address
Internal writing
signal
Counter clearing
signal
FRC
N
H'0000
T1
T2
Writing cycle with the FRC
φ
Figure 16.13 Competition between Writing and Clearing with the FRC