Rev. 1.0, 02/00, page 298 of 1141
Bit 5
Enabling the TMRI1 Interrupt (TMRI1E): This bit works to permit/prohibit occurrence
of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of
the TMRU-1.
Bit 5
TMRI1E
Description
0
Prohibits occurrences of TMRI1 interrupts
(Initial value)
1
Permits occurrences of TMRI1 interrupts
Bit 4
TMRI3 Interrupt Requesting Flag (TMRI3): This is the TMRI3 interrupt requesting
flag.
It indicates occurrence of an interrupt cause being selected by the CP/SLM bit of the TMRM2,
such as occurrences of the TMRU-2 capture signals or ending of the slow tracking mono-multi
processing.
Bit 4
TMRI3
Description
0
[Clearing conditions]
(Initial value)
When 0 is written after reading 1
1
[Setting conditions]
At occurrence of the interrupt cause being selected by the CP/SLM bit of the TMRM2
Bit 3
TMRI2 Interrupt Requesting Flag (TMRI2): This is the TMRI2 interrupt requesting
flag.
It indicates occurrences of the TMRU-2 underflow signals or ending of the acceleration/braking
processing of the capstan motor.
Bit 3
TMRI2
Description
0
[Clearing conditions]
(Initial value)
When 0 is written after reading 1
1
[Setting conditions]
At occurrences of the TMRU-2 underflow signals or ending of the acceleration
/braking processing of the capstan motor