Rev. 1.0, 02/00, page 777 of 1141
27.2.7
H Complement and Mask Timing Register (HCMMR)
15
0
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1 HC0 HM6 HM5 HM4 HM3 HM2 HM1 HM0
W
14
0
W
13
12
0
W
0
W
11
0
W
10
0
W
9
0
W
8
0
W
7
0
W
6
0
W
5
0
W
4
0
W
3
0
W
2
0
W
1
0
W
0
0
W
Bit :
Initial value :
R/W :
The HCMMR is a 16-bit write-only register for specifying the timing (Th: Hsync frequency) for
generating a complementary pulse when a pulse in the Hsync signal is lost, and the timing (Tm
and Tm2) for clearing the HHK (masking period).
The HC8 to HC0 bits specify the timing for generating a complementary pulse; if no Hsync pulse
is input within this specified time, a complementary pulse is generated from the H complement
and mask counter. When a supplementary pulse is generated, the HHK function, provided for
resetting the H supplement mask counter, remains cleared, and the H supplement mask counter is
synchronized with the Hsync signal at the next Hsync pulse input. The HHK2 operation for
generating the Hsync signal (OSCH) for the AFC circuit is performed when a supplementary pulse
is generated.
The HM6 to HM0 bits specify the timing for clearing the HHK function. Set the HHK clearing
timing to about 85% of the Hsync period starting from the SEPH rising edge to eliminate
equalizing pulses and copy-guard signals.
Figure 27.12 shows the complement and mask timing. The HHK signal is set to 1 about 5
µ
s after
the SEPH rising edge, and the HHK2 signal is set to 1 immediately after the H complement and
mask counter is reset. The HHK signal is also used for the noise detection window. For details on
the noise detection, refer to section 27.2.8, Noise Detection Counter (NDETC).
When reset, the HCMMR is initialized to H'0000.
