Rev. 1.0, 02/00, page 779 of 1141
Bits 6 to 0
HHK Period Setting (HM6 to HM0): Specify the timing for clearing the HHK
(masking period) for the Hsync signal. The H complement and mask counter starts counting at a
rising edge of the SEPH signal; the HHK period specified by these bits starts at this timing. This
value is also used as the timing for resetting the noise detection window signal. Note that the
setting precision is the upper six bits of the H complement and mask counter: the lower two bits of
the counter are ignored.
The following shows an example of HM6 to HM0 settings.
Condition:
(HM + 1)
×
(8/OSC) > 54
µ
s (about 85% of the Hsync period
)
System clock OSC = 10 MHz
8/OSC: 1.25 MHz (0.8
µ
s
)
Example:
To set the timing to 54
µ
s
54
µ
s / 0.8
µ
s = 67.5
HM6 to HM0 value = H'44 (67)
27.2.8
Noise Detection Counter (NDETC)
0
0
0
0
0
0
0
0
7
R
NC0
0
R
NC7
6
R
NC6
5
R
NC5
4
R
NC4
3
R
NC3
2
R
NC2
1
R
NC1
Bit :
Initial value :
R/W :
The NDETC is a 10-bit read-only counter of which the upper eight bits can be read. This counter
counts the number of Hsync cycles in which an Hsync pulse (noise H) is input while the noise
detection window signal is 1, and counts the number of Hsync cycles in which no Hsync pulse is
input while the noise detection window signal is 0. When this counter value matches the noise
detection level, the noise detection interrupt request flag is set. The counter is reset at every other
vertical sync signal (AFCV signal) input; that is, the noise status for one field can be monitored.
The NDETC value can be read by the CPU; the noise status can be monitored by the read value.
When reset, the NDETC is initialized to H'00. The NDETC is assigned to the same address as the
NDETR. Figure 27.13 shows the timing for noise detection.
