S5PC110_UM
2 IIS MULTI AUDIO INTERFACE
2-6
2.4.1.1 External DMA Transfer
To transfer up to 5.1 channel primary sound from s/w mixer to IIS, use external DMA or SFR interface. To play
primary sound for 5.1 channels or record 2 channel sound, IIS has TXFIFO0, TXFIFO1, TXFIFO2, TXFIFO_S and
RXFIFO registers. IIS will mix primary sound in TXFIFO0 and secondary sound in TXFIFO_S and output mixed
sound stream to external codec logic.
In the external DMA transfer mode, use external DMA controller to access the transmitter or receiver FIFO. The
transmitter or receiver FIFO state activates DMA service request internally. The FTXEMPT, FRXEMPT, FTXFULL,
and FRXFULL bits of I2SCON register represent the transmitter or receiver FIFO data state. Especially,
FTXEMPT and FRXFULL bit are the ready flag for DMA service request; the transmit DMA service request is
activated when TXFIFO is not empty and the receiver DMA service request is activated when RXFIFO is not full.
The external DMA transfer uses only handshaking method for single data. Note that during external DMA
acknowledge activation; the data read or write operation should be performed.
* Reference: DMA request point
•
TX mode: (FIFO is not full) & (TXDMACTIVE is active)
•
RX mode: (FIFO is not empty) & (RXDMACTIVE is active)
2.4.1.2 Internal DMA Transfer
To transfer up to 2 channel secondary sound to IIS, use internal DMA or SFR interface. To play secondary sound
for 2 channels, internal DMA in IIS gets sound data from address range between 0xC000_0000 and
0xC01F_FFFF (when ARM decodes encoded music file.) or between OBUF0 and OBUF1 (when RP decodes
encoded music file.) to TXFIFO_S. IIS will mix primary sound in TXFIFO0 and secondary sound in TXFIFO_S and
output mixed sound stream to external codec logic.
Like external DMA transfer mode, in the internal DMA transfer mode, the internal DMA is activated when
TXFIFO_S is not full. After activation, internal DMA runs according to SFR configurations and signals an interrupt
after completion.
•
It only supports single transfer in both Internal & External DMA transfer mode.
•
Refer OBUF0 and OBUF1 at 10.01.S5PC110_Low Power Audio Subsystem chapter.
2.4.1.3 Sound Mixing
IIS can mix primary sound in TXFIFO0 and secondary sound in TXFIFO_S when two sound sources have the
same sampling rate and PCM format.
•
If overflow occurs, then mixer saturates output value.
•
Mixer can handle Different Bit Length. (Controlled by BLC bit at IISMOD SFR)
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...