S5PC110_UM
2 1BCAMERA INTERFACE
2-68
MSCTRLn
Bit
Description
R/W
Initial State
SEL_DMA_
CAM
[3]
Selects input data selection.
0 = External camera input path
1 = Memory data input path (Input DMA)
(ML=OX)
R/W 0
InFormat_M
[2:1]
Specifies the source image format for input DMA.
00 = YCbCr 4:2:0 input image format. (2 or 3 plane)
01 = YCbCr 4:2:2 input image format. (2 or 3 plane)
(ref. 2 or 3 plane format register
→
C_INT_IN)
10 = YCbCr 4:2:2 input image format. (1 plane)
11 = RGB input image format. (ref. RGB format register
→
InRGB_FMT)
Note) Refer to the gathering extension register.
YCbCr444_IN
(ML=OX)
R/W 0
ENVID_M
[0]
Starts input DMA operation (Software setting triggers low to
high). The hardware clears automatically. If data flows from
input DMA to local direct FIFO, the software can clear this
bit when LCD_ENSTATUS is ‘0’.
1) SEL_DMA_CAM = ‘0’, ENVID_M don’t care (using
external camera signal)
2) SEL_DMA_CAM = ‘1’, ENVID_M is set (0
→
1), then
Input DMA operation starts
(ML=OX)
R/W 0
NOTE:
ENVID_M SFR must be set at the end. Starting order for using DMA input path.
SEL_DMA_CAM (others SFR setting)
→
Image Capture Enable and Scaler start SFR setting
→
ENVID_M SFR
setting.
•
Cf.) Image Capture Enable SFR must be set at the end. Starting order for using Direct FIFO input path.
SEL_DMA_CAM
→
SelWB_CAMIF (others SFR setting)
→
Image Capture Enable and Scaler start SFR
setting
•
Cf.) Image Capture Enable SFR be set at last. Starting order for using camera input path.
SEL_DMA_CAM
→
SelWB_CAMIF
→
SelCam_CAMIF (others SFR setting)
→
Image Capture Enable
and Scaler start SFR setting
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...