Samsung S5PC110, Manual

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S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
1-5
1.3.5 TX/RX FIFO TRIGGER LEVEL AND DMA BURST SIZE IN DMA MODE
If Tx/Rx data reaches the Tx/Rx FIFO trigger level of UFCONn register in DMA mode, the DMA transaction starts.
A single DMA transaction transfers a data whose size is specified as the DMA burst size of UCONn register, and
the DMA transactions are repeated until transferred data size reaches the Tx/Rx FIFO trigger level. Thus, DMA
burst size should be less than or equal to Tx/Rx FIFO trigger level. In general, it is recommended to ensure that
Tx/Rx FIFO trigger level and DMA burst size matches.
1.3.6 RS-232C INTERFACE
To connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI
signals are required. You can control these signals with general I/O ports using software because the AFC does
not support the RS-232C interface.
1.3.7 INTERRUPT/DMA REQUEST GENERATION
Each UART in S5PC110 comprises of seven status (Tx/Rx/Error) signals, namely, Overrun error, Parity error,
Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty. These
conditions are indicated by the corresponding UART status register (UTRSTATn/UERSTATn).
The Overrun Error, Parity Error, Frame Error and Break Condition specify the receive error status. If receive-error-
status-interrupt-enable bit is set to 1 in the control register (UCONn), the receive error status generates receive-
error-status-interrupt. If a receive-error-status-interrupt-request is detected, you can identify the source of interrupt
by reading the value of UERSTATn.
If the receiver transfers data of the receive shifter to the receive FIFO register in FIFO mode, and the number of
received data is greater than or equal to the Rx FIFO Trigger Level, Rx interrupt is generated if Receive mode in
control register (UCONn) is set to 1 (Interrupt request or polling mode).
In Non-FIFO mode, transferring the data of receive shifter to receive holding register causes Rx interrupt in the
Interrupt request and polling modes.
If the transmitter transfers data from its transmit FIFO register to transmit shifter and the number of data left in
transmit FIFO is less than or equal to the Tx FIFO Trigger Level, Tx interrupt is generated (provided Transmit
mode in control register is selected as Interrupt request or polling mode). In Non-FIFO mode, transferring the data
from transmit holding register to transmit shifter causes Tx interrupt in the Interrupt request and polling mode.
Remember that the Tx interrupt is always requested if the number of data in the transmit FIFO is smaller than the
trigger level. This means that an interrupt is requested as soon as you enable the Tx interrupt, unless you fill the
Tx buffer. It is recommended to fill the Tx buffer first and then enable the Tx interrupt.
The interrupt controllers of S5PC110 are of the level-triggered type. You must set the interrupt type as ‘Level’ if
you program the UART control registers.
If Receive and Transmit modes in control register are selected as DMAn request mode, then DMAn request
occurs instead of Rx or Tx interrupt in the above situation.