S5PC110_UM
2 1BCAMERA INTERFACE
2-66
2.8.2.18 Input DMA Control Register (MSCTRLn)
•
MSCTRL0, Address = 0xFB20_00FC
•
MSCTRL1, Address = 0xFB30_00FC
•
MSCTRL2, Address = 0xFB40_00FC
MSCTRLn
Bit
Description
R/W
Initial State
Weave_in
[31]
Even and Odd fields can be read separately from a
complete progressive frame. The 1st frame reads even field
data and the 2nd frame reads odd field data. When 1st and
2nd frame operation finish, InputDMA is disabled. Both
Weave_in and Interlace_out should be set in simultaneous
frames. Also, it is recommended that pingpong address
should not be changed at Interlace even/ odd field
(BC_SEL field should 0) .
0 = Weave
1 = Normal
Note)
When using input rotator in Weave_in mode, output
horizontal size should be even value. Because vertical data
will be converted into horizontal one after rotating.
(ML=XX)
R/W 0
Reserved [30:28]
Reserved
R/W 0
Successive_cnt [27:24] Specifies
input
DMA burst successive count (Default is 4
but 3, 2, or 1 are also possible). This value should not be
‘0’.
(ML=OX)
R/W 4’d4
Reserved [23:20]
Reserved
R/W 0
InBuf_Mode
[19]
Specifies input DMA buffer address mode.
1 = Ping-Pong buffer mode (Address 0 and 1 are valid)
0 = Single buffer mode (Only address 0 is valid)
(ML=OX)
R/W 0
Reserved [18]
Reserved
R/W 0
Order2p_in
[17:16] Specifies YCbCr 4:2:0 or 4:2:2 2plane memory reading
style order in source input DMA image.
Bit
MSB
LSB
00 Cr3Cb3Cr2Cb2Cr1Cb1Cr0Cb0
01 Cb3Cr3Cb2Cr2Cb1Cr1Cb0Cr0
10 Reserved
11 Reserved
(ML=OX)
R/W 0
C_INT_IN
[15]
1 = YCbCr 4:2:0 or 4:2:2 2plane input format
R/W
0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...