Samsung S5PC110, Manual

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S5PC110_UM 7 6BTVOUT & VIDEO DAC
7-7
The internal pixel rate is 13.5 MHz which is 1/4 times of 54 MHz video clock which is used for DAC. With 13.5
MHz pixel rate, the horizontal blanking timing and active video timing are defined as follows:
Sample Rate = 13.5 MHZ
16 Samples
Digital
Blanking
138 Samples
(0-137)
Digital Active Line
720 Samples
(138-857)
Total Line
858 Samples
(0-857)
Figure 7-5 Horizontal Blanking and Active Video Timing @ 525/60 Hz
Sample Rate = 13.5 MHZ
12 Samples
Digital
Blanking Digital Active Line
Total Line
144 Samples
(0-143)
720 Samples
(144-863)
864 Samples
(0-863)
Figure 7-6 Horizontal Blanking and Active Video Timing @ 625/50 Hz
VIDEO [3:0] bits in SDO_CONFIG register controls all the timing signals in TG module. Finally note that all the
internal counters and discrete time oscillators operate with 54 MHz video clock. The hsync, vsync, field_id, and
data request signals are generated and used internally at 54 MHz rate. If they are delivered to ‘DispPipe’ module
their timings are re-synchronized with 135 MHz system clock.