Samsung S5PC110, Manual

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S5PC110_UM 1 0BDISPLAY CONTROLLER
1-68
VIDCON0 Bit Description Initial State
1 = Start of a frame (only once per frame)
Reserved [15:14] Reserved. 0
CLKVAL_F [13:6] Determines the rates of VCLK and CLKVAL[7:0].
VCLK = HCLK / (1), where CLKVAL >= 1
Notes.
1. The maximum frequency of VCLK is 66MHz.
2. CLKSEL_F register selects Video Clock Source. 0
VCLKFREE [5] Controls VCLK Free Run (Only valid at RGB IF mode).
0 = Normal mode (controls using ENVID)
1 = Free-run mode 0
CLKDIR [4] Selects the clock source as direct or divide using CLKVAL_F
register.
0 = Direct clock (frequency of VCLK = frequency of Clock
source)
1 = Divided by CLKVAL_F 0x00
Reserved [3] Should be 0. 0x0
CLKSEL_F [2] Selects the video clock source.
0 = HCLK
1 = SCLK_FIMD
HCLK is the bus clock, whereas SCLK_FIMD is the special clock
for display controller.
For more information, refer to Chapter, “02.03 CLOCK
CONTROLLER”. 0
ENVID [1] Enables/ disables video output and logic immediately.
0 = Disables the video output and display control signal.
1 = Enables the video output and display control signal. 0
ENVID_F [0] Enables/ disables video output and logic at current frame end.
0 = Disables the video output and display control signal.
1 = Enables the video output and display control signal.
* If this bit is set to “on” and “off”, then “H” is read and video
controller is enabled until the end of current frame. 0
NOTE:
Display On: ENVID and ENVID_F are set to “1”.
Direct Off: ENVID and ENVID_F are set to “0” simultaneously.
Per Frame Off: ENVID_F is set to “0” and ENVID is set to “1”.
Caution:
1: If VIDCON0 is set for Per Frame Off in interlace mode, the value of INTERLACE_F should be set to
“0” in the same time.
2: If display controller is off using direct off, it is impossible to turn on the display controller without
reset.