Samsung S5PC110, Manual

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S5PC110_UM 1 DMA CONTROLLER
1-30
1.3.2.2 Interrupts
DMAC provides IRQ signals for use as level sensitive interrupts to external CPUs. If you program the Interrupt
Enable Register to generate an interrupt after DMAC executes DMASEV, it sets the corresponding IRQ as high.
You can clear the interrupt by writing to the Interrupt Clear Register.
To control the interrupt, follow these steps:
1. Set up the Interrupt Enable Register to generate interrupts.
− The interrupt enable register is a 32-bit register. Each bit of the INTEN register checks whether the DMAC
signals an interrupt using the corresponding IRQ.
− Program the appropriate bit to control the DMAC response on execution of DMASEV.
o
Bit [N] = 0: If executing DMASEV for event N, then the DMAC signals event N to all the threads.
o
Bit [N] = 1 If executing DMASEV for event N, then the DMAC sets irq[N] as HIGH.
2. To set the corresponding IRQ HIGH by executing DMASEV, program assembly code.
− Use DMASEV instruction means an interrupt using one of the IRQ outputs.
3. Clear the interrupt by writing to the Interrupt Clear Register.
− Each bit in the INTCLR register controls the clearing of an interrupt.
− Program to control the clearing of the IRQ outputs:
o
Bit [N] = 0: The status of irq[N] does not change. Bit [N] = 1: The DMAC sets irq[N] as low.
o
If DMA is set to fault status, an interrupt occurs.
1.3.2.3 Summary
1. You can configure the DMAC with up to eight DMA channels, with each channel being capable of supporting a
single concurrent thread of DMA operation. In addition, there is a single DMA manager thread to initialize the
DMA channel thread.
2. Channel thread
− A. Each channel thread can operate the DMA. You must write assembly code accordingly. If you need a
number of independent DMA channels, you must write a number of assembly codes for each channel.
− B. Assemble them, link them into one file, and load this file into memory.