Samsung S5PC110, Manual

Page: 1917 / 2426

S5PC110_UM 6 SPDIF TRANSMITTER
6-11
6.6.1.1 SPDIFOUT Clock Control Register (SPDCLKCON, R/W, Address = 0XE110_0000)
SPDCLKCON Bit Description Initial State
- [31:3] Reserved 0
Main Audio Clock Selection [2] 0 = Internal clock (I_MCLK_INT)
1 = External clock (I_MCLK_EXT) 0
SPDIFOUT clock down ready
(read only)
[1] 0 = Clock-down not ready
1 = Clock-down ready
1
SPDIFOUT power on [0] 0 = Power off
1 = Power on
0
6.6.1.2 SPDIFOUT Control Register (SPDCON, R/W, Address = 0XE110_0004)
SPDCON Bit Description Initial State
- [31:27] Reserved 0
FIFO Level [26:22] FIFO Level Monitoring (Read Only)
FIFO depth is 16
*0 = Empty of FIFO Level, 16 = Full of FIFO Level
00000
FIFO Level Threshold [21:19] FIFO Threshold Level is controllable
000 = 0-FIFO Level
001 = 1-FIFO Level
010 = 4-FIFO Level
011 = 6-FIFO Level
100 = 10-FIFO Level
101 = 12-FIFO Level
110 = 14-FIFO Level
111 = 15-FIFO Level
000
FIFO transfer mode [18:17] 00 = DMA transfer mode
01 = Polling mode
10 = Interrupt mode
11 = Reserved
00
FIFO_level Interrupt Status [16] Read Operation
0 = No interrupt pending.
1 = Interrupt pending.
Write Operation
0 = No effect.
1 = Clear this flag.
0
FIFO_level Interrupt Enable [15] 0 = Interrupt masked
1 = Interrupt enable
0
endian format [14:13] 00 = big endian
o_data = {in_data[23:0]}
01 = 4 byte swap
o_data={in_data[15:8], in_data[23:16],
in_data[31:24]}
0