Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-6
There is second option in DEEP-IDLE mode for low-power MP3 playback, i.e., TOP block and SUB block is
power-gated, but Audio block is still power ”ON”.
This time is measured from wakeup event assertion to ARM reset de-assertion or ARM clock supply. That is, ARM
runs the next instruction this time after wakeup event is asserted. Restored time is not included. Those saved data
in external memory should be restored after this time. All values are measured assuming 12 MHz clock as main
OSC.
Wake-up time in this case refers to time to power-up a power domain.
For TOP block ”ON”, 1us for ARM clock supply
For TOP block ”OFF”, max 300us for PLL+ 100us for ARM reset de-assertion
Maximum 300us for PLL + 50 us for ARM clock supply
For TOP block ”OFF”, maximum 300us for PLL + 100 us for ARM reset de-assertion
6ms for regulator ”ON” + 100us for ARM reset de-assertion
1ms for OSC+ max 300us for PLL + 50 us for ARM clock supply
For TOP block ”OFF”, 1ms for OSC + max 300us for PLL + 100 us for ARM reset de-assertion
6ms for regulator ”ON” + 1ms for OSC + 100us for ARM reset de-assertion
Internal power is connected to all internal logic except CPU, ALIVE, and RTC module, as shown in
Table 4-2
.
Alive power is connected to ALIVE module in
Table 4-2
.
In SLEEP mode, power for all blocks except ALIVE block is not supplied since regulator or PMIC turn “OFF” the
external power source, and all PLLs and unnecessary oscillators are disabled. Static power consumption is very
small in SLEEP mode. The only leakage power source is due to power supplied to ALIVE block.
Hardware disables the PLL in STOP and SLEEP mode, and OSCs are selectively disabled by setting OSC_EN
field of STOP_CFG and SLEEP_CFG register in SYSCON.