Samsung S5PC110, Manual

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S5PC110_UM 2 ADVANCED CRYPTO ENGINE
2.2.2.2 DMA Configuration
Each DMA has three main parameters, namely:
• STARTADDR (32-bit): Specifies the start address of DMA. The address does not need to be aligned by 32-bit.
Its value increases by four after every transaction.
• LENGTH (32-bit): Specifies the block length of DMA. The length need not be aligned by 32-bit. Its value
decreases by four after every transaction.
• FLUSH (1-bit): If this bit is high, then data flushes out from FIFO and DMA. After flushing, the start address
keeps the stopped address and the length is 0. The flushing state should be released by writing value ‘0’ to
this bit.
2.2.2.3 Interrupt Controller (for DMA Interrupt)
Figure 2-7
shows the interrupt controller scheme for one interrupt signal. Each of the four DMA interrupt signals
have the following control scheme, that is, each interrupt signal is generated by a DMA in pulse form and latched
by the FCINTPEND register to form a level sensitive interrupt signal.
The latched signal is masked by FCINTENSET register in bit-by-bit form. Each bit in FCINTENSET can be set by
writing ‘1’ to the corresponding bit in FCINTENSET, and cleared by writing ‘1’ to the corresponding bit in
FCINTENCLR.
Figure 2-7 Interrupt Controller Scheme for one Interrupt Signal
2-7