Samsung S5PC110, Manual

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S5PC110_UM 1 DMA CONTROLLER
1-20
1.2.1.4 Configuration Register1 for DMA_PERI(0,1) (CR1, R)
• CR1 for DMA_PERI0, R, Address = 0xE090_0E04
• CR1 for DMA_PERI1, R, Address = 0xE0A0_0E04
CR1 Bit Description Initial State
num_i-cache_lines [7:4] The read value is always 7. It means DMA_PERI(0,1) has 8 i-
cache lines.
0x7
i-cache_len [2:0] The read value is always 4. It means the length of an i-cache
line is 16 bytes.
0x4
* PL330 contains a built-in instruction cache controller.
1.2.1.5 Configuration Register2 for DMA_PERI(0,1) (CR2, R)
• CR2 for DMA_PERI0, R, Address = 0xE090_0E08
• CR2 for DMA_PERI1, R, Address = 0xE0A0_0E08
CR2 Bit Description Initial State
boot_addr [31:0] Provides the value of boot_addr[31:0] when the DMAC exits
from reset.
32’b0
0
* The first DMAC instruction fetch is to the address specified by DMA PC at reset value.
1.2.1.6 Configuration Register3 for DMA_PERI(0,1) (CR3, R)
• CR3 for DMA_PERI0, R, Address = 0xE090_0E0C
• CR3 for DMA_PERI1, R, Address = 0xE0A0_0E0C
CR3 Bit Description Initial State
INS [31:0] Specifies the security state of interrupt outputs.
Bit [N] = 1: Assigns irq[N] to non-secure state.
32’hffff_ffff
0xFFFF_FFFF