Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-42
1.4.1.14 PHY Status Register (PhyStatus, Read Only, Address=0xF000_0040, 0xF140_0040)
PHYSTATUS0 Bit Description R/W
Initial
State
Reserved [31:14] Should be zero 0x0
ctrl_lock_value [13:4] Locked Delay
Locked delay line encoding value
ctrl_lock_value[9:2]: number of delay cells for coarse lock
ctrl_lock_value[1:0]: control value for fine lock
R 0x0
Reserved [3] Should be zero 0x0
ctrl_locked [2] DLL Lock
0 = Unlocks DLL
1 = Locks DLL
R 0x0
ctrl_flock [1] Fine Lock Information
It is indicated that DLL is locked with fine resolution, “phase
offset error” is less than 80ps. R 0xX
ctrl_clock [0] Coarse Lock Information
It is indicated that DLL changes step delays of the “delay line”
and “phase offset error” is less than 160ps.
R 0xX