Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-55
OTHERS Bit Description Initial State
1 = RELEASE_RET_UART_IO
For more information on list of PADs belonging to
UART I/O pad, refer to Section 4.2 PIN SUMMARY of
GPIO manual.
Reserved [27:18] Reserved 0x000
ARM_PRESETn_TYPE [17] ARM_PRESETn type selection
0 = Asserted when software reset is generated.
1 = Not asserted when software reset is generated. 0
Reserved [16:10] Reserved 0x00
CLKOUT [9:8] Control the XCLKOUT signal output. This bit is prior to
CLK_OUT register value. When this bit is ‘10’ or ‘11’,
XCLKOUT output selected clock is not only normal
mode but also Top block off status and sleep mode.
00 = Clock out signal from SYSCON
(by CLK_OUT SFR of CMU)
01 = Reserved
10 = XXTI (Main X-tal input)
11 = XUSBXTI (USB X-tal input) 0x0
Reserved [7:2] Reserved 0x00
CLEAR_DBGACK [1] Clear DBGACK signal when this field has value 1.
Cortex-A8 asserts DBGACK signal to indicate the
system has entered DEBUG state. If DBGACK is
asserted, this state is stored in PMU until software
clears it using this field. 0
SYSCON_INT_DISABLE [0] Disables new interrupt to reach processor core.
Active HIGH.
Setting this field to HIGH is a mandatory step when
entering low-power mode.
This field is automatically cleared when low-power
mode entering sequence is completed. 0
4.10.5.2 MISC Register (OM_STAT, R, Address = 0xE010_E100)
OM_STAT Bit Description Initial State
Reserved [31:6] Reserved 0x000_0000
OM [5:0] Operation mode value 0x00