Samsung S5PC110, Manual

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S5PC110_UM 6 5BMULTI FORMAT CODEC
6-10
6.3 REGISTER DESCRIPTION
6.3.1 REGISTER MAP
Register Address R/W Description Reset Value
Control Registers
MFC_SW_RESET 0xF170_0000 R/W Soft reset for each module in MFC. Each
bit has following interpretation.
0 = Reset
1 = Release
0x000003fe
MFC_RISC_HOST_INT 0xF170_0008 R/W MFC to host interrupt register.
An interrupt is raised when MFC enables
the INTERRUPT bit. Host CPU needs to
check this register, properly process an ISR
(Interrupt Service Routine), and clear the
INTERRUPT bit.
0x00000000
MFC_HOST2RISC_
COMMAND 0xF170_0030 R/W Host to MFC command register.
Host can send command to MFC to open
instance or close instance.
0x00000000
MFC_HOST2RISC_ARG1 0xF170_0034 R/W The first argument of the host command 0x00000000
MFC_HOST2RISC_ARG2 0xF170_0038 R/W The second argument of the host command 0x00000000
MFC_HOST2RISC_ARG3 0xF170_003C R/W Context memory address 0x00000000
MFC_HOST2RISC_ARG4 0xF170_0040 R/W Context memory size 0x00000000
MFC_RISC2HOST_
COMMAND 0xF170_0044 R/W MFC to host command register.
MFC can respond to host using the
MFC_RISC2HOST_COMMAND register
0x00000000
MFC_RISC2HOST_ARG1 0xF170_0048 R/W MFC to host argument register.
This register is used with the
MFC_RISC2HOST_COMMAND register
0x00000000
MFC_RISC2HOST_ARG2 0xF170_004C R/W The second argument of the host command 0x00000000
MFC_RISC2HOST_ARG3 0xF170_0050 R/W The Third argument of the host command 0x00000000
MFC_RISC2HOST_ARG4 0xF170_0054 R/W The fourth argument of the host command 0x00000000
MFC_FIRMWARE_
VERSION 0xF170_0058 R Firmware version information register 0x00000000
DBG_INFO_OUTPUT1 0xF170_0064 R Debug information output register 1 0x00000000
DBG_INFO_OUTPUT1 0xF170_0068 R Debug information output register 2 0x00000000
MFC_FIRMWARE_STAT
US 0xF170_0080 R Firmware status register 0x00000000
MFC_MC_DRAMBASE_
ADDR_A 0xF170_0508 R/W DRAM base address which indicates the
base address for the memory map of the
port A
0xD3000000