Samsung S5PC110, Manual

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S5PC110_UM 3 ONENAND CONTROLLER
3-6
The corresponding commands must be issued to the device command register (Command register (device
address offset: 0x1E440)). For more information about the OneNAND device memory map, refer to
Figure 3-3
that
shows the data path when the external AHB master accesses control registers.
Table 3-1 OneNAND Controller Memory Map
OneNAND Controller
Address (Start)
OneNAND Controller
Address (End)
Window
Size
Note
0xB0000000 0xB001FFFF 128KB
OneNAND nCE[0]
(For more information about
OneNAND Chip #0 address
map, refer to
Table 3-3
.
0xB0020000 0xB003FFFF 128KB Reserved for future use
0xB0040000 0xB005FFFF 128KB OneNAND nCE[1]
0xB0060000 0xB007FFFF 128KB Reserved for future use
0xB0080000 0xB009FFFF 128KB Reserved for future use
0xB00A0000 0xB00BFFFF 128KB Reserved for future use
0xB00C0000 0xB00DFFFF 128KB Reserved for future use
0xB00E0000 0xB00FFFFF 128KB Reserved for future use
0xB0100000 0xB011FFFF 128KB Reserved for future use
0xB0120000 0xB013FFFF 128KB Reserved for future use
0xB0140000 0xB015FFFF 128KB Reserved for future use
0xB0160000 0xB017FFFF 128KB Reserved for future use
0xB0180000 0xB019FFFF 128KB Reserved for future use
0xB01A0000 0xB01BFFFF 128KB Reserved for future use
0xB01C0000 0xB01DFFFF 128KB Reserved for future use
OneNAND
Interface
0xB01E0000 0xB01FFFFF 128KB Reserved for future use
Reserved 0xB0200000 0xB03FFFFF 2MB Reserved for future use
Reserved 0xB0400000 0xB05FFFFF 2MB Reserved for future use
Control
Registers
0xB0600000 0xB07FFFFF 2MB 32-bit Registers
Reserved 0xB0800000 0xB0FFFFFF 8MB Reserved for future use