Samsung S5PC110, Manual

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S5PC110_UM 1 BUS CONFIGURATION
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BUS CONFIGURATION
1.1 OVERVIEW OF BUS CONFIGURATION
This chapter describes the bus configuration in S5PC110.
1.1.1 AXI INTERCONNECT
S5PC110 consists of 12 high-performance AXI interconnect. The role of AXI interconnect is to interconnect bus
masters to bus slaves.
1.1.1.1 Key Features of AXI Interconnect
The key features of AXI interconnect include:
•
Quality of Service
The Quality of Service (QoS) scheme tracks the number of outstanding transactions. When a specified
number is reached, it permits transactions from specified masters only. This scheme only provides support for
slaves that have a combined acceptance capability such as the Dynamic Memory Controller (DMC).
The QoS scheme has no effect until the AXI interconnect matrix calculates the following:
At a particular Master Interface (MI), there are a number of outstanding transactions equal to the value stored in
QoS tidemark.
It then accepts transactions only from slave ports specified in the QoS access control. This restriction remains
until the number of outstanding transactions is again less than the value stored in QoS tidemark.
Figure 1-1
shows the implementation for an interconnect supporting two masters and one slave.