Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-34
Figure 4-4
shows the clock behaviour during the power-on reset sequence. The crystal oscillator begins oscillation
within several milliseconds after the power supply supplies enough power-level to the S5PC110. Internal PLLs are
disabled after power-on reset is asserted. XnRESET signal should be released after the fully settle-down of the
power supply-level. For the proper system operation, the S5PC110 requires a hazard-free system clock (SYSCLK,
ARMCLK, HCLK and PCLK) when the system reset is released (XnRESET). However, since PLLs are disabled,
Fin (the direct external oscillator clock) is fed directly to SYSCLK instead of the MPLL_CLK (PLL output) before
the S/W configures the MPLLCON register to enable the operation of PLLs. If new P/M/S values are required, the
S/W configures P/M/S field first, and the PLL_EN field later.
The PLL begins the lockup sequence toward the new frequency only after the S/W configures the PLL with a new
frequency-value. SYSCLK is configured to be PLL output (MPLL_CLK) immediately after lock time.
The user should be aware that the crystal oscillator settle-down time is not explicitly added by the hardware during
the power-up sequence. The S5PC110 assumes that the crystal oscillation is settled during the power-supply
settle-down period. However, to ensure the proper operation during wake-up from the STOP mode, the S5PC110
explicitly adds the crystal oscillator settle-down time (the wait-time can be programmed using the OSC_STABLE
registers) after wake-up from the STOP mode.
S5PC110 has four PLLs, namely, APLL, MPLL, EPLL, and VPLL.
•
APLL: used to generate ARM clock
•
MPLL: used to generate system bus clock and several special clocks
•
EPLL: used to generate several special clocks
•
VPLL: used to generate Video clocks. Usually, generates 54 MHz.
Power-off transition NORMAL mode Wake-up from SLEEP SLEEP mode NORMAL mode
XnRESET
XPWRRGTON
VDD
ALIVE
VDD
INT
/
VDD
ARM
VDD
IO
XXTI
1.1V
OSC
_STABLE
(internal)
RESETn
max
(OSC_STABLE,
PWR_STABLE)
>
0ns
>
>
0ns
>
3.3V/2.5V/1.8V
0.6V
1.1V
Power-on transition
0ns 0ns
Figure 4-4 Power-ON/OFF Reset Sequence