S5PC110_UM
1 0BDISPLAY CONTROLLER
1-82
1.5.2.11 Window 2 Control Register (WINCON2, R/W, Address = 0xF800_0028)
WINCON2
Bit
Description
Initial State
BUFSTATUS_H [31] Specifies
the Buffer Status (read only).
Note. BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L}
00 = Buffer set 0
01 = Buffer set 1
10 = Buffer set 2
0
BUFSEL_H
[30]
Selects the Buffer set.
Note. BUFSEL = {BUFSEL_H, BUFSEL_L}
00 = Buffer set 0
01 = Buffer set 1
10 = Buffer set 2 (only available when BUF_MODE == 1’b1)
0
LIMIT_ON
[29]
Enables CSC source limiter (for clamping xvYCC source).
0 = Disables
1 = Enables (when local SRC data has xvYCC color space,
InRGB=1)
0
EQ709 [28]
Controls
CSC
parameter.
0 = Eq.601
1 = Eq.709 (when local SRC data has HD (709) color gamut)
0
nWide/Narrow
[27:26] Chooses color space conversion equation from YCbCr to RGB
based on the input value range (2’00 for YCbCr Wide range and
2’11 for YCbCr Narrow range).
- Wide Range: Y/ Cb/ Cr: 255-0
- Narrow Range: Y: 235-16, Cb/ Cr: 240-16
00
Reserved [25:24]
Reserved
00
Reserved
[23]
Should be ‘0’.
0
ENLOCAL_F [22]
Selects
the Data access method.
0 = Dedicated DMA
1 = Local Path
0
BUFSTATUS_L [21]
Specifies
the Buffer Status (read only).
Note: BUFSTATUS = {BUFSTATUS_H, BUFSTATUS_L}
BUFSEL_L
[20]
Selects the Buffer set.
Note: BUFSEL = {BUFSEL_H, BUFSEL_L}
0
BUFAUTOEN
[19]
Specifies the Double Buffer Auto control bit.
0 = Fixed by BUFSEL
1 = Auto changed by Trigger Input
0
BITSWP_F
[18]
Specifies the Bit swap control bit.
0 = Swap Disable
1 = Swap Enable
Note: It should be 0 when ENLOCAL is 1.
0
BYTSWP_F
[17]
Specifies the Byte swaps control bit.
0 = Swap Disable
1 = Swap Enable
Note: It should be 0 when ENLOCAL is 1.
0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...