Samsung S5PC110, Manual

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S5PC110_UM 3 CLOCK CONTROLLER
3-21
3.7.2.2 PLL Control Registers (MPLL_CON, R/W, Address = 0xE010_0108)
MPLL_CON Bit Description Initial State
ENABLE [31] PLL enable control (0: disable, 1: enable) 0
Reserved [30] Reserved 0
LOCKED [29] PLL locking indication
0 = Unlocked
1 = Locked
Read Only 0
Reserved [28] Reserved 0
VSEL [27] VCO frequency range selection 0x0
Reserved [26] Reserved 0
MDIV [25:16] PLL M divide value 0x14D
Reserved [15:14] Reserved 0
PDIV [13:8] PLL P divide value 0x3
Reserved [7:3] Reserved 0
SDIV [2:0] PLL S divide value 0x1
The reset value of APLL_CON0 and MPLL_CON generates 800 MHz and 667 MHz output clock respectively, if
the input clock frequency is 24 MHz.
Equation to calculate the output frequency:
FOUT = MDIV X FIN / (PDIV X 2
SDIV
)
where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :
PDIV: 1
≤
PDIV
≤
63
MDIV: 16
≤
MDIV
≤
511
SDIV: 0
≤
SDIV
≤
5
Fref (=FIN / PDIV): 1MHz
≤
Fref
≤
10MHz
FVCO (=MDIV X FIN / PDIV):
1000MHz
≤
FVCO
≤
1400MHz when VSEL=LOW.
1400MHz
≤
FVCO
≤
2000MHz when VSEL=HIGH.
FOUT:
32MHz
≤
FOUT
≤
2000MHz
Refer to
3.3.2 Recommended PLL PMS Value for MPLL
for recommended PMS values.
Caution:
MPLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop,
sleep mode. MPLL will be automatically turned off while entering those low-power modes.