Samsung S5PC110, Manual

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S5PC110_UM 7 SD/MMC CONTROLLER
7-91
7.10.25 CONTROL REGISTERS 3 REGISTER
7.10.25.1 FIFO Interrupt Control (Control Register 3)
•
CONTROL3_0, R/W, Address = 0xEB00_0084
•
CONTROL3_1, R/W, Address = 0xEB10_0084
•
CONTROL3_2, R/W, Address = 0xEB20_0084
•
CONTROL3_3, R/W, Address = 0xEB30_0084
CONTROL3 Bit Description Initial State
FCSEL3 [31] Feedback Clock Select [3]
Reference
(1)
0x0
FIA3 [30:24] FIFO Interrupt Address register 3
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x7F) generates at 512-byte(128-word) position. 0x7F
FCSEL2 [23] Feedback Clock Select [2]
Reference
(1)
0x0
FIA2 [22:16] FIFO Interrupt Address register 2
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x5F) generates at 384-byte(96-word) position. 0x5F
FCSEL1 [15] Feedback Clock Select [1]
Reference
(2)
0x0
FIA1 [14:8] FIFO Interrupt Address register 1
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x3F) generates at 256-byte(64-word) position. 0x3F
FCSEL0 [7] Feedback Clock Select [0]
Reference
(2)
0x0
FIA0 [6:0] FIFO Interrupt Address register 0
FIFO (512Byte Buffer memory, word address unit)
Initial value (0x1F) generates at 128-byte(32-word) position. 0x1F
NOTE:
1. FCSel[3:2] : Tx Feedback Clock Delay Control : Inverter delay means 10ns delay if SDCLK 50MHz setting
'00', '01' = Inverter delay, '10', '11' = basic delay(aroujnd 2ns)
2. FCSel[1:0] : Rx Feedback Clock Delay Control : Inverter delay means10ns delay if SDCLK 50MHz setting
'00', '01' = Inverter delay, '10', '11' = basic delay(aroujnd 2ns)
3. Tx Feedback inversion setting (FCSel[3:2] = '00' or '01'), Tx Feedback clock enable (ENFBCLKTX = 0) and
Normal Speed mode (OUTEDGEINV = 0) setting make Tx data transfer mismatch (Do not set).