Samsung S5PC110, Manual

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S5PC110_UM 7 SD/MMC CONTROLLER
7-17
1. Set the value corresponding to the executed data byte length of one block to Block Size register.
2. Set the value corresponding to the executed data block count to Block Count register.
3. Set the value corresponding to the issued command to Argument register.
4. Set the value to Multi / Single Block Select and Block Count Enable. At this time, set the value corresponding
to the issued command to Data Transfer Direction, Auto CMD12 Enable and DMA Enable.
5. Set the value corresponding to the issued command to Command register.
NOTE:
If the upper byte is written in the Command register, it issues a SD command
6. Wait for the Command Complete Interrupt.
7. Write 1 to the Command Complete (STACMDCMPLT) in the Normal Interrupt Status register to clear this bit.
8. Read Response register and get necessary information in accordance with the issued command.
9. If this sequence is for write to a card, proceed to step (10-W). If read from a card, go to step (10-R).
10. (10-W) Wait for Buffer Write Ready Interrupt.
11. (11-W) Write 1 to the Buffer Write Ready (STABUFWTRDY) in the Normal Interrupt Status register to clear
this
bit.
12. (12-W) Write block data (in according to the number of bytes specified at the step (1)) to Buffer Data Port
register.
13. (13-W) Repeat until all blocks are sent and then go to step (14).
14. (10-R) Wait for the Buffer Read Ready Interrupt.
15. (11-R) Write 1 to the Buffer Read Ready (STABUFRDRDY) in the Normal Interrupt Status register to clear this
bit.
16. (12-R) Read block data (in according to the number of bytes specified at the step (1)) from the Buffer Data
Port
register.
17. (13-R) Repeat until all blocks are received and proceed to step (14).
18. (14) If this sequence is for Single or Multiple Block Transfer, proceed to step (15). In case of Infinite Block
Transfer, go to step (17).
19. (15) Wait for Transfer Complete Interrupt.
20. (16) Write 1 to the Transfer Complete (STATRANCMPLT) in the Normal Interrupt Status register to clear this
bit.
21. (17) Perform the sequence for Abort Transaction.
NOTE:
Step (1) and Step (2) can be executed at same time. Step (4) and Step (5) can be executed at same time